Microchip Technology WINC3400 ATWINC3400-MR210CA User Manual Manual

Microchip Technology Inc. ATWINC3400-MR210CA Manual

Contents

Manual

 ATWINC3400-MR210CA IEEE 802.11 b/g/n Network Controller Module withIntegrated Bluetooth Low Energy 4.0IntroductionThe ATWINC3400-MR210CA is an IEEE 802.11 b/g/n RF/Baseband/Medium Access Control (MAC)network controller module with Bluetooth Low Energy technology that is compliant with Bluetooth version4.0. This module is optimized for low power and high performance mobile applications. This modulefeatures small form factor when integrating Power Amplifier (PA), Low-Noise Amplifier (LNA), Transmit/Receive (T/R) switch (for Wi-Fi and Bluetooth), Power Management Unit (PMU), and Chip Antenna. TheATWINC3400-MR210CA module requires a 32.768 kHz clock for Sleep operation.The ATWINC3400-MR210CA module utilizes highly optimized IEEE 802.11 Bluetooth coexistenceprotocols, and provides Serial Peripheral Interface (SPI) to interface with the host controller.FeaturesWi-Fi features:• IEEE 802.11 b/g/n RF/PHY/MAC• IEEE 802.11 b/g/n (1x1) with single spatial stream, up to 72 Mbps PHY rate in 2.4 GHz ISM band• Integrated chip antenna• Superior sensitivity and range via advanced PHY signal processing• Advanced equalization and channel estimation• Advanced carrier and timing synchronization• Supports Soft-AP• Supports IEEE 802.11 WEP, WPA, and WPA2• Superior MAC throughput through hardware accelerated two-level A-MSDU/A-MPDU frameaggregation and block acknowledgment• On-chip memory management engine to reduce the host load• Operating temperature range from -40°C to +85°C• Wi-Fi Alliance® certified for connectivity and optimizations– ID: WFA62065• Integrated on-chip microcontroller• SPI host interface• Integrated Flash memory for Wi-Fi and Bluetooth system software• Low leakage on-chip memory for state variables• Fast AP re-association (150 ms)• On-chip network stack to offload MCU– Integrated network IP slack to minimize the host CPU requirements• Network features: Firmware version 1:2:x© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 1
– TCP, UDP, DHCP, ARP, HTTP, SSL, DNS, and SNTPBluetooth features:• Bluetooth 4.0 (Bluetooth Low Energy) certifications– Controller QD ID - 77870– Host QD ID - 77451• Class 2 transmission• Adaptive Frequency Hopping (AFH)• Superior sensitivity and range ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 2
Table of ContentsIntroduction......................................................................................................................1Features.......................................................................................................................... 11. Ordering Information and Module Marking................................................................ 52. Block Diagram........................................................................................................... 63. Pinout and Package Information............................................................................... 73.1. Package Description.................................................................................................................. 104. Electrical Characteristics..........................................................................................114.1. Absolute Maximum Ratings........................................................................................................114.2. Recommended Operating Conditions........................................................................................ 114.3. DC Characteristics..................................................................................................................... 124.4. IEEE 802.11 b/g/n Radio Performance...................................................................................... 124.5. Bluetooth Radio Performance.................................................................................................... 144.6. Timing Characteristics................................................................................................................ 165. Power Management................................................................................................ 215.1. Device States............................................................................................................................. 215.2. Controlling Device States........................................................................................................... 215.3. Power-Up/Down Sequence........................................................................................................ 225.4. Digital I/O Pin Behavior During Power-Up Sequences...............................................................236. Clocking...................................................................................................................246.1. Low-Power Clock....................................................................................................................... 247. CPU and Memory Subsystem................................................................................. 257.1. Processor................................................................................................................................... 257.2. Memory Subsystem....................................................................................................................257.3. Nonvolatile Memory....................................................................................................................258. WLAN Subsystem................................................................................................... 278.1. MAC........................................................................................................................................... 278.2. PHY............................................................................................................................................288.3. Radio..........................................................................................................................................289. Bluetooth Low Energy 4.0....................................................................................... 3010. External Interfaces...................................................................................................3110.1. Interfacing with the Host Microcontroller.................................................................................... 3110.2. SPI Interface...............................................................................................................................3210.3. UART Interface...........................................................................................................................3411. Application Reference Design................................................................................. 35© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 3
11.1. Host Interface - SPI.................................................................................................................... 3512. Module Outline Drawings........................................................................................ 3713. Design Consideration.............................................................................................. 3813.1. Module Placement and Routing Guidelines............................................................................... 3813.2. Antenna Performance................................................................................................................ 3914. Reflow Profile Information....................................................................................... 4114.1. Storage Condition.......................................................................................................................4114.2. Solder Paste...............................................................................................................................4114.3. Stencil Design............................................................................................................................ 4114.4. Baking Conditions...................................................................................................................... 4114.5. Soldering and Reflow Condition................................................................................................. 4115. Module Assembly Considerations........................................................................... 4416. Regulatory Approval................................................................................................4516.1. United States..............................................................................................................................4516.2. Canada.......................................................................................................................................4616.3. Europe........................................................................................................................................4816.4. Other Regulatory Information..................................................................................................... 4917. Reference Documentation.......................................................................................5018. Document Revision History..................................................................................... 51The Microchip Web Site................................................................................................ 52Customer Change Notification Service..........................................................................52Customer Support......................................................................................................... 52Product Identification System........................................................................................53Microchip Devices Code Protection Feature................................................................. 53Legal Notice...................................................................................................................53Trademarks................................................................................................................... 53Quality Management System Certified by DNV.............................................................54Worldwide Sales and Service........................................................................................55 ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 4
1.  Ordering Information and Module MarkingThe following table provides the ordering details for the ATWINC3400-MR210CA module.Table 1-1. Ordering DetailsModel Number Ordering Code Package Description RegulatoryInformationATWINC3400-MR210CAATWINC3400-MR210CAxxx 122.43 x14.73 x 2.0mmCertifiedmodule withchip antennaFCC, IC, CE 2Note: 1. 'xxx' in the preceding table and following figure denotes the software version. Order code changesas per the software version. For example, current version of the software is v1.22, so its equivalentorder code is ATWINC3400-MR210CA122.2. CE certification pending.The following figure illustrates the ATWINC3400-MR210CA module marking information.Figure 1-1. Marking Information MR 2 1 0CDevice nameMR: Industrial2: OTA with shield1: Reserved1: ReservedC: Chip antennaRevision letterSoftware versionATWINC3400 A xxx  ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 5
2.  Block DiagramThe following figure shows the block diagram of the ATWINC3400-MR210CA module.Figure 2-1. ATWINC3400-MR210CA Module Block DiagramATWINC3400 IC ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 6
3.  Pinout and Package InformationThis package contains an exposed paddle that must be connected to the system board ground. TheATWINC3400-MR210CA module pin assignment is shown in following figure.Figure 3-1. ATWINC3400-MR210CA Module Pin AssignmentATWINC3400-MR210CAMODULEJ1J2J3J4J5J6J7J8J9J10J11J12J13J14J15J16J17J18J19J20J21J22J23J24J25J26J27J28J29J30J31J32J33J34J35J36 GNDI2C_SDA_MI2C_SCL_MIRQNGPIO20GPIO19GPIO18GPIO17GNDGPIO7SPI_MOSISPI_SSNSPI_MISOSPI_SCKGPIO8GNDRTC_CLKCHIP_ENVBATUART_RXDUART_TXDGPIO4GPIO3GNDVDDIOBT_RXDBT_TXDRESETNN/CN/CN/CN/CSPI_CFGGNDI2C_SDA_SI2C_SCL_SThe following table provides the ATWINC3400-MR210CA module pin description. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 7
Table 3-1. ATWINC3400-MR210CA Module Pin DescriptionPin # Pin Name Pin Type Description1 GND GND Ground pin.2 SPI_CFG Digital Input Serial Peripheral Interface pin, which must bedied to VDDIO.3 NC - No connection.4 NC - No connection.5 NC - No connection.6 NC - No connection.7 RESETN Digital Input • Active-low hard Reset pin.• When the Reset pin is asserted low, themodule is in the Reset state. When theReset pin is asserted high, the modulefunctions normally.• This pin must connect to a host outputthat is low by default on power-up. If thehost output is tri-stated, add a 1 MOhmpull down resistor to ensure a low level atpower-up.8 BT_TXD Digital I/O,Programmable pull upBluetooth UART transmit data output pin.9 BT_RXD Digital I/O,Programmable pull upBluetooth UART receive data input pin.10 I2C_SDA_S Digital I/O,Programmable pull up• I2C Slave data pin.• Used only for debug developmentpurposes. It is recommended to add atest point for this pin.• I2C is the default configuration. <TBD>11 I2C_SCL_S Digital I/O,Programmable pull up• I2C Slave clock pin.• Used only for debug developmentpurposes. It is recommended to add atest point for this pin.• I2C is the default configuration. <TBD>12 VDDIO Power Digital I/O power supply.13 GND GND Ground pin.14 GPIO3 Digital I/O,Programmable pull upGeneral Purpose Input/Output pin.15 GPIO4 Digital I/O,Programmable pull upGeneral Purpose Input/Output pin. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 8
Pin # Pin Name Pin Type Description16 UART_TXD Digital I/O,Programmable pull up• Wi-Fi UART TxD output pin.• Used only for debug developmentpurposes. It is recommended to add atest point for this pin.17 UART_RXD Digital I/O,Programmable pull up• Wi-Fi UART RxD input pin.• Used only for debug developmentpurposes. It is recommended to add atest point for this pin.18 VBAT Power Power supply pin for DC/DC converter and PA.19 CHIP_EN Digital Input • PMU enable pin.• When the CHIP_EN pin is asserted high,the module is enbled. When theCHIP_EN pin is asserted low, the moduleis disabled or put into Power-Down mode.• Connect to a host output that is low bydefault at power-up. If the host output istri-stated, add a 1 MOhm pull downresistor if necessary to ensure a low levelat power-up.20 RTC_CLK Digital I/O,Programmable pull up• RTC Clock input pin.• This pin must connect to a 32.768 kHzclock source.21 GND GND Ground pin.22 GPIO8 Digital I/O,Programmable pull upGeneral Purpose Input/Output pin.23 SPI_SCK Digital I/O,Programmable pull upSPI clock pin.24 SPI_MISO Digital I/O,Programmable pull upSPI MISO (Master In Slave Out) pin.25 SPI_SSN Digital I/O,Programmable pull upActive-low SPI SSN (Slave Select) pin.26 SPI_MOSI Digital I/O,Programmable pull upSPI MOSI (Master Out Slave In) pin.27 GPIO7 Digital I/O,Programmable pull upGeneral Purpose Input/Output pin.28 GND GND Ground pin.29 GPIO17 Digital I/O,Programmable pull upGeneral Purpose Input/Output pin.30 GPIO18 Digital I/O,Programmable pull upGeneral Purpose Input/Output pin. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 9
Pin # Pin Name Pin Type Description31 GPIO19 Digital I/O,Programmable pull upGeneral Purpose Input/Output pin.32 GPIO20 Digital I/O,Programmable pull upGeneral Purpose Input/Output pin.33 IRQN Digital output,Programmable pull up• ATWINC3400-MR210CA module hostinterrupt request output pin.• This pin must connect to a host interruptpin.34 I2C_SCL_M Digital I/O,Programmable pull upI2C Master clock pin.35 I2C_SDA_M Digital I/O,Programmable pull upI2C Master data pin.36 GND GND Ground pin.37 PADDLE VSS Power Connect to system board ground.3.1  Package DescriptionThe following table provides the ATWINC3400-MR210CA module package dimensions.Table 3-2. ATWINC3400-MR210CA Module Package InformationParameter Value UnitPad count 36 -Package size 22.43 x 14.73 mmTotal thickness 2.09Pad pitch 1.20Pad width 0.81Exposed pad size 4.4 x 4.4 ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 10
4.  Electrical CharacteristicsThis chapter provides an overview of the electrical characteristics of the ATWINC3400-MR210CAmodule.4.1  Absolute Maximum RatingsThe following table provides the absolute maximum ratings for the ATWINC3400-MR210CA module.Table 4-1. ATWINC3400-MR210CA Module Absolute Maximum RatingsSymbol Parameter Min. Max. UnitVDDIO I/O supply voltage -0.3 5.0 VVBAT Battery supply voltage -0.3 5.0VIN Digital input voltage -0.3 VDDIOVAIN Analog input voltage -0.3 1.5VESDHBM Eelectrostatic dischageHuman Body Model(HBM)-1000, -2000 (seenotes below)+1000, +2000 (seenotes below)TAStorage temperature -65 150 ºC- Junction temperature - 125- RF input power - 23 dBm1. VIN corresponds to all the digital pins.2. For VESDHBM, each pin is classified as Class 1, or Class 2, or both:2.1. The Class 1 pins include all the pins (both analog and digital).2.2. The Class 2 pins include all digital pins only.2.3. VESDHBM is ±1 kV for Class 1 pins. VESDHBM is ± 2 kV for Class 2 pins.Caution:  Stresses beyond those listed under “Absolute Maximum Ratings” cause permanentdamage to the device. This is a stress rating only. The functional operation of the device atthose or any other conditions above those indicated in the operation listings of this specificationis not implied. Exposure to maximum rating conditions for extended periods affects the devicereliability.4.2  Recommended Operating ConditionsThe following table provides the recommended operating conditions for the ATWINC3400-MR210CAmodule. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 11
Table 4-2. ATWINC3400-MR210CA Module Recommended Operating ConditionsSymbol Parameter Min. Typ. Max. UnitsVDDIO I/O supply voltage (1) 2.7 3.3 3.6 VVBAT Battery supply voltage(2)(3) 3.0 3.6 4.2 V- Operating temperature -40 - 85 ºCNote: 1. I/O supply voltage is applied to the VDDIO pin.2. Battery supply voltage is applied to the VBAT pin.3. The ATWINC3400-MR210CA module is functional across this range of voltages; however, optimalRF performance is guaranteed for VBAT in the range ≥ 3.0V VBAT ≤ 4.2V.4.3  DC CharacteristicsThe following table provides the DC characteristics for the ATWINC3400-MR210CA module digital pads.Table 4-3. DC Electrical CharacteristicsSymbol Parameter Min Typ Max UnitVIL Input LowVoltage-0.30 - 0.60 VVIH Input HighVoltageVDDIO-0.60 - VDDIO+0.30VOL Output LowVoltage- - 0.45VOH Output HighVoltageVDDIO-0.50 - -- Output LoadCapacitance- - 20 pF- Digital InputLoadCapacitance- - 64.4  IEEE 802.11 b/g/n Radio Performance4.4.1  Receiver PerformanceThe receiver performance is tested under following conditions:• VBAT = 3.3V• VDDIO = 3.3V• Temp = 25°C• Measured after RF matching networkThe following table provides the receiver performance characteristics for the ATWINC3400-MR210CAmodule. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 12
Table 4-4. IEEE 802.11 Receiver Performance CharacteristicsParameter Description Min. Typ. Max. UnitFrequency - 2,412 - 2,472 MHzSensitivity 802.11b 1 Mbps DSSS - -95.0 - dBm2 Mbps DSSS - -93.5 -5.5 Mbps DSSS - -90.0 -11 Mbps DSSS - -86.0 -Sensitivity 802.11g 6 Mbps OFDM - -90.0 - dBm9 Mbps OFDM - -88.5 -12 Mbps OFDM - -86.0 -18 Mbps OFDM - -84.5 -24 Mbps OFDM - -82.0 -36 Mbps OFDM - -78.5 -48 Mbps OFDM - -74.5 -54 Mbps OFDM - -73.0 -Sensitivity 802.11n(BW=20 MHz,800ns GI)MCS 0 - -89.0 - dBmMCS 1 - -87.0 -MCS 2 - -84.0 -MCS 3 - -81.5 -MCS 4 - -78.0 -MCS 5 - -74.0 -MCS 6 - -72.0 -MCS 7 - -70.0 -Maximum receivesignal level1-11 Mbps DSSS - 0 - dBm6-54 Mbps OFDM - 0 -MCS 0 - 7 (800ns GI) - 0 -Adjacent channelrejection1 Mbps DSSS (30 MHz offset) - 50 - dB11 Mbps DSSS (25 MHz offset) - 43 -6 Mbps OFDM (25 MHz offset) - 40 -54 Mbps OFDM (25 MHz offset) - 25 -MCS 0 – 20 MHz BW (25 MHzoffset)- 40 -MCS 7 – 20 MHz BW (25 MHzoffset)- 20 - ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 13
4.4.2  Transmitter PerformanceThe transmitter performance is tested under following conditions:• VBAT = 3.3V• VDDIO = 3.3V• Temp = 25°CThe following table provides the transmitter performance characteristics for the ATWINC3400-MR210CAmodule.Table 4-5. IEEE 802.11 Transmitter Performance CharacteristicsParameter Description Minimum Typical Max. UnitFrequency - 2,412 - 2,472 MHzOutput power 802.11b 1 Mbps - 16.7(1) - dBm802.11b 11 Mbps - 17.5(1) -802.11g OFDM 6 Mbps - 18.3(1) -802.11g OFDM 54 Mbps - 13.0(1) -802.11n HT20 MCS 0 (800nsGI)- 17.5(1) -802.11n HT20 MCS 7 (800nsGI)- 12.5(1) -Tx power accuracy - - ±1.5(2) - dBCarrier suppression - - 30.0 - dBcHarmonic outputpower (Radiated,Regulatory mode)2nd - - -41 dBm/MHz3rd - - -41Note: 1. Measured at IEEE 802.11 specification compliant EVM/Spectral mask.2. Measured after RF matching network.3. Operating temperature range is -40°C to +85°C. RF performance guaranteed at room temperatureof 25°C with a 2-3dB change at boundary conditions.4. With respect to Tx power, different (higher/lower) RF output power settings may be used for specificantennas and/or enclosures, in which case recertification may be required.5. The availability of some specific channels and/or operational frequency bands are countrydependent and should be programmed at the host product factory to match the intendeddestination. Regulatory bodies prohibit exposing the settings to the end user. This requirementneeds to be taken care of via host implementation.4.5  Bluetooth Radio Performance4.5.1  Receiver PerformanceThe receiver performance is tested under following conditions:• VBAT = 3.3V ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 14
• VDDIO = 3.3V• Temp: 25°C• Measured after RF matching network.The following table provides the Bluetooth receiver performance characteristics for the ATWINC3400-MR210CA module.Table 4-6. Bluetooth Receiver Performance CharacteristicsParameter Description Min. Typ. Max. UnitFrequency - 2,402 - 2,480 MHzSensitivity (ideal Tx) Bluetooth Low Energy (GFSK) - -92.5 - dBmMaximum receive signallevelBluetooth Low Energy (GFSK) - -3.5 -Interference performance(Bluetooth Low Energy)Co-channel - 12 dBadjacent + 1 MHz - 0 -adjacent - 1 MHz - 3 -adjacent + 2 MHz(imagefrequency)- -25 -adjacent - 2 MHz - -41 -adjacent + 3 MHz (adjacent toimage)- -35 -adjacent - 3 MHz - -35 -adjacent + 4 MHz - -45 -adjacent - 4 MHz - -30 -adjacent +5 MHz - -34 -adjacent - 5 MHz - -30 -4.5.2  Transmitter PerformanceThe transmitter performance is tested under following conditions:• VBAT = 3.3V• VDDIO = 3.3V• Temp: 25°C• Measured after RF matching network.The following table provides the Bluetooth transmitter performance characteristics for the ATWINC3400-MR210CA module.Table 4-7. Bluetooth Transmitter Performance CharacteristicsParameter Description Min. Typ. Max. UnitFrequency - 2,402 - 2,480 MHzOutput power Bluetooth Low Energy (GFSK) - 3.2 3.7 dBm ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 15
Parameter Description Min. Typ. Max. UnitIn-band spuriousemission (Bluetooth LowEnergy)N+2 (Image frequency) - -33 -N + 3 (Adjacent to imagefrequency)- -32 -N-2 - -50 -N-3 - -49 -4.6  Timing Characteristics4.6.1  I2C Slave TimingThe I2C Slave timing diagram for the ATWINC3400-MR210CA module is shown in the following figure.Figure 4-1. I2C Slave Timing DiagramThe following table provides the I2C Slave timing parameters for the ATWINC3400-MR210CA module.Table 4-8. I2C Slave Timing ParametersParameter Symbol Min. Max. Units RemarksSCL Clock Frequency fSCL 0 400 kHz -SCL Low Pulse Width tWL 1.3 -µs-SCL High Pulse Width tWH 0.6 - -SCL, SDA Fall Time tHL - 300ns-SCL, SDA Rise Time tLH - 300 This is dictated byexternal componentsSTART Setup Time tSUSTA 0.6 -µs-START Hold Time tHDSTA 0.6 - -SDA Setup Time tSUDAT 100 - ns -SDA Hold Time tHDDAT 0 - ns Slave and Master Default ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 16
Parameter Symbol Min. Max. Units Remarks40 - µs Master ProgrammingOptionSTOP Setup Time tSUSTO 0.6 -µs-Bus Free Time BetweenSTOP and START tBUF 1.3 - -Glitch Pulse Reject tPR 0 50 ns -4.6.2  SPI Slave TimingThe SPI Slave timing for the ATWINC3400-MR210CA module is provided in the following figures.Figure 4-2. SPI Slave Clock Polarity and Clock Phase Timing ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 17
Figure 4-3. SPI Slave Timing DiagramThe following table provides the SPI Slave timing parameters for the ATWINC3400-MR210CA module.Table 4-9. SPI Slave Timing Parameters (1)Parameter Symbol Min. Max. UnitClock Input Frequency (2) fSCK - 48 MHzClock Low Pulse Width tWL 6 - nsClock High Pulse Width tWH 4 -Clock Rise Time tLH 0 7Clock Fall Time tHL 0 7TXD Output Delay (3) tODLY 3 9 from SCK fall11 from SCK riseRXD Input Setup Time tISU 3 -RXD Input Hold Time tIHD 5 - ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 18
Parameter Symbol Min. Max. UnitSSN Input Setup Time tSUSSN 5 -SSN Input Hold Time tHDSSN 5 -Note: 1. Timing is applicable to all SPI modes.2. Maximum clock frequency specified is limited by the SPI Slave interface internal design; actualmaximum clock frequency can be lower and depends on the specific PCB layout.3. Timing based on 15 pF output loading.4.6.3  SPI Master TimingThe SPI Master timing for the ATWINC3400-MR210CA module is shown in the following figure.Figure 4-4. SPI Master Timing DiagramThe following table provides the SPI Master timing parameters for the ATWINC3400-MR210CA module .Table 4-10. SPI Master Timing Parameters (1)Parameter Symbol Min. Max. UnitClock Output Frequency (2) fSCK - 20 MHzClock Low Pulse Width tWL 19 - nsClock High Pulse Width tWH 21 -Clock Rise Time (3) tLH - 11Clock Fall Time (3) tHL - 10RXD Input Setup Time tISU 24 -RXD Input Hold Time tIHD 0 -SSN/TXD Output Delay (3) tODLY -5 3Note:  ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 19
1. Timing is applicable to all SPI modes.2. Maximum clock frequency specified is limited by the SPI Master interface internal design; actualmaximum clock frequency can be lower and depends on the specific PCB layout.3. Timing based on 15 pF output loading. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 20
5.  Power Management5.1  Device StatesThe ATWINC3400-MR210CA module has multiple device states, based on the state of the IEEE 802.11and Bluetooth subsystems. It is possible for both subsystems to be active at the same time. To simplifythe device power consumption breakdown, the following basic states are defined. One subsystem can beactive at a time:• WiFi_ON_Transmit – Device actively transmits IEEE 802.11 signal• WiFi_ON_Receive – Device actively receives IEEE 802.11 signal• BT_ON_Transmit – Device actively transmits Bluetooth signal• BT_ON_Receive – Device actively receives Bluetooth signal• Doze – Device is powered on but it does not actively transmit or receive data• Power_Down – Device core supply is powered off5.2  Controlling Device StatesThe following table shows different device states and its power consumption. The device states can beswitched using the following:• CHIP_EN – Module pin (pin 19) enables or disables the DC/DC converter• VDDIO – I/O supply voltage from external supplyIn the ON states, VDDIO is ON and CHIP_EN is high (at VDDIO voltage level). To change from the ONstates to Power_Down state, connect the RESETN and CHIP_EN pin to logic low (GND) by following thepower-down sequence mentioned in Figure 5-1. When VDDIO is OFF and CHIP_EN is low, the chip ispowered off with no leakage.Table 5-1. ATWINC3400-MR210CA Device States Current ConsumptionDevice State Code Rate Output Power(dBm)Current Consumption(1)IVBAT IVDDIOON_WiFi_Transmit 802.11b 1 Mbps 16.7 271 mA 24 mA802.11b 11 Mbps 17.5 265 mA 24 mA802.11g 6 Mbps 18.3 275 mA 24 mA802.11g 54 Mbps 13.0 235 mA 24 mA802.11n MCS 0 17.5 272 mA 24 mA802.11n MCS 7 12.5 232 mA 24 mAON_WiFi_Receive 802.11b 1 Mbps N/A 63.9 mA 23.7 mA802.11b 11 Mbps N/A 63.9 mA 23.7 mA802.11g 6 Mbps N/A 63.9 mA 23.7 mA802.11g 54 Mbps N/A 63.9 mA 23.7 mA802.11n MCS 0 N/A 63.9 mA 23.7 mA ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 21
Device State Code Rate Output Power(dBm)Current Consumption(1)IVBAT IVDDIO802.11n MCS 7 N/A 63.9 mA 23.7 mAON_BT_Transmit(@3.2 dBm Pout)BLE 4.0 1 Mbps 1.5 79.37 mA 23.68 mAON_BT_Receive BLE 4.0 1 Mbps N/A 51.36 mA 23.68 mADoze (Bluetooth LowEnergy Idle)N/A N/A 53 mA (2)Doze (Bluetooth LowEnergy Low Power)N/A N/A 1 mA (2)Power_Down N/A N/A 10.5 uA(2)Note: 1. Conditions: VBAT = 3.3V, VDDIO = 3.3V, at 25°C.2. Current consumption mentioned for these states is the sum of current consumed in VDDIO andVBAT voltage rails.When power is not supplied to the device (DC/DC converter output and VDDIO are OFF, at groundpotential), voltage cannot be applied to the ATWINC3400-MR210CA module pins because each pincontains an ESD diode from the pin to supply. This diode turns on when voltage higher than one diode-drop is supplied to the pin.If voltage must be applied to the signal pads when the chip is in a low-power state, the VDDIO supplymust be ON, so the Power_Down state must be used. Similarly, to prevent the pin-to-ground diode fromturning ON, do not apply voltage that is more than one diode-drop below the ground to any pin.5.3  Power-Up/Down SequenceThe following figure illustrates the power-up/down sequence for the ATWINC3400-MR210CA module.Figure 5-1.  Power-Up/Down SequencetCtBtAVBATTVDDIOCHIP_ENRESETNXO ClocktC'tB'tA'The following table provides power-up/down sequence timing parameters. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 22
Table 5-2.  Power-Up/Down Sequence TimingParameter Min. Max. UnitsDescription NotestA0 - ms VBAT rise toVDDIO riseVBAT and VDDIO can rise simultaneously orconnected together. VDDIO must not rise beforeVBAT.tB0 - ms VDDIO rise toCHIP_EN riseCHIP_EN must not rise before VDDIO. CHIP_ENmust be driven high or low and must not be leftfloating.tC5 - ms CHIP_EN rise toRESETN riseThis delay is required to stabilize the XO clockbefore RESETN removal. RESETN must be drivenhigh or low and must not be left floating.tA’ 0 - ms VDDIO fall toVBAT fallVBAT and VDDIO fall simultaneously or connectedtogether. VBAT must not fall before VDDIO.tB’ 0 - ms CHIP_EN fall toVDDIO fallVDDIO must not fall before CHIP_EN. CHIP_ENand RESETN must fall simultaneously.tC’ 0 - ms RESETN fall toVDDIO fallVDDIO must not fall before RESETN. RESETNand CHIP_EN fall simultaneously.5.4  Digital I/O Pin Behavior During Power-Up SequencesThe following table represents the digital I/O pin states corresponding to the device power modes.Table 5-3. Digital I/O Pin Behavior in Different Device StatesDevice State VDDIO CHIP_ENRESETNOutput Driver InputDriverPull Up/DownResistor (96kOhm)Power_Down: core supplyOFFHigh Low Low Disabled (Hi-Z) Disabled DisabledPower-On Reset: coresupply and hard reset ONHigh High Low Disabled (Hi-Z) Disabled EnabledPower-On Default: coresupply ON, device out ofreset and not programmedHigh High High Disabled (Hi-Z) Enabled EnabledOn_Doze/ On_Transmit/On_Receive: core supplyON, device programmed byfirmwareHigh High High Programmedby firmware foreach pin:enabled ordisabledOppositeofOutputDriverstateProgrammed byfirmware foreach pin:enabled ordisabled ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 23
6.  Clocking6.1  Low-Power ClockThe ATWINC3400-MR210CA module requires an external 32.768 kHz clock to be supplied at the modulepin 20. This clock is used during the sleep operation. The frequency accuracy of this external clock mustbe within ±200 ppm. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 24
7.  CPU and Memory Subsystem7.1  ProcessorThe ATWINC3400-MR210CA module has two Cortus APS3 32-bit processors, one is used for Wi-Fi andthe other is used for Bluetooth. In IEEE 802.11 mode, the processor performs many of the MAC functions,including but not limited to: association, authentication, power management, security key management,and MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes ofoperation, such as Station (STA) and Access Point (AP) modes. In Bluetooth mode, the processorhandles multiple tasks of the Bluetooth protocol stack.7.2  Memory SubsystemThe APS3 core uses a 256 KB instruction/boot ROM (160 KB for IEEE 802.11 and 96 KB for Bluetooth)along with a 420 KB instruction RAM (128 KB for IEEE 802.11 and 292 KB for Bluetooth), and a 128 KBdata RAM (64 KB for IEEE 802.11 and 64 KB for Bluetooth). In addition, the device uses a 160 KBshared/exchange RAM (128 KB for IEEE 802.11 and 32 KB for Bluetooth), accessible by the processorand MAC, which allows the processor to perform various data management tasks on the Tx and Rx datapackets.7.3  Nonvolatile MemoryThe ATWINC3400-MR210CA module has 768 bits of nonvolatile eFuse memory that can be read by theCPU after device reset. This nonvolatile One-Time-Programmable (OTP) memory can be used to storecustomer-specific parameters, such as 802.11 MAC address and Bluetooth address; various calibrationinformation such as Tx power, crystal frequency offset, and other software-specific configurationparameters. The eFuse is partitioned into six 128-bit banks. The bit map of the first and last banks isshown in the following figure. The purpose of the first 80 bits in bank 0 and the first 56 bits in bank 5 isfixed, and the remaining bits are general-purpose software dependent bits, reserved for future use.Currently, the Bluetooth address is derived from the Wi-Fi MAC address (BT_ADDR=MAC_ADDR+1).This eliminates the need to program the first 56 bits in bank 5. Since each bank and each bit can beprogrammed independently, this allows for several updates of the device parameters following the initialprogramming. For example, if the MAC address has to be changed, Bank 1 has to be programmed withthe new MAC address along with the values of Tx gain correction and frequency offset if they are usedand programmed in the Bank 0. The contents of Bank 0 have to be invalidated in this case byprogramming the Invalid bit in the Bank 0. This will allow the firmware to use the MAC address from Bank1.By default, ATWINC3400-MR210CA modules are programmed with the MAC address and the frequencyoffset bits of Bank 0. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 25
Figure 7-1.  ATWINC3400-MR210CA eFuse Bit Map ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 26
8.  WLAN SubsystemThe WLAN subsystem is composed of the Media Access Controller (MAC), Physical Layer (PHY), andthe radio.8.1  MACThe ATWINC3400-MR210CA module is designed to operate at low power, while providing high datathroughput. The IEEE 802.11 MAC functions are implemented with a combination of dedicated datapathengines, hardwired control logic, and a low power, high-efficiency microprocessor. The combination ofdedicated logic with a programmable processor provides optimal power efficiency and real time responsewhile providing the flexibility to accommodate evolving standards and future feature enhancements.The dedicated datapath engines are used to implement datapath functions with heavy computationalrequirements. For example, a Frame Check Sequence (FCS) engine checks the Cyclic RedundancyCheck (CRC) of the transmitting and receiving packets, and a cipher engine performs all the requiredencryption and decryption operations for the WEP, WPA-TKIP, and WPA2 CCMP-AES securityrequirements.Control functions, which have real time requirements, are implemented using hardwired control logicmodules. These logic modules offer real time response while maintaining configurability through theprocessor. Examples of hardwired control logic modules are the channel access control module(implements EDCA/HCCA, Beacon Tx control, interframe spacing, and so on), protocol timer module(responsible for the Network Access vector, back-off timing, timing synchronization function, and slotmanagement), MAC Protocol Data Unit (MPDU) handling module, aggregation/deaggregation module,block ACK controller (implements the protocol requirements for burst block communication), and Tx/Rxcontrol Finite State Machine (FSM) (coordinates data movement between PHY and MAC interface, cipherengine, and the Direct Memory Access (DMA) interface to the Tx/Rx FIFOs).The following are the characteristics of MAC functions implemented solely in software on themicroprocessor:• Functions with high memory requirements or complex data structures. Examples includeassociation table management and power save queuing.• Functions with low computational load or without critical real time requirements. Examples includeauthentication and association.• Functions that require flexibility and upgradeability. Examples include beacon frame processing andQoS scheduling.FeaturesThe ATWINC3400-MR210CA MAC supports the following functions:• IEEE 802.11b/g/n• IEEE 802.11e WMM QoS EDCA/HCCA/PCF multiple access categories traffic scheduling• Advanced IEEE 802.11n features:– Transmission and reception of aggregated MPDUs (A-MPDU)– Transmission and reception of aggregated MSDUs (A-MSDU)– Immediate block acknowledgment– Reduced Interframe Spacing (RIFS)• IEEE 802.11i and WFA security with key management: ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 27
– WEP 64/128– WPA-TKIP– 128-bit WPA2 CCMP (AES)• Advanced power management:– Standard IEEE 802.11 power save mode• RTS-CTS and CTS-self support• Either STA or AP mode in the infrastructure basic service set mode8.2  PHYThe ATWINC3400-MR210CA module WLAN PHY is designed to achieve reliable and power-efficientphysical layer communication specified by IEEE 802.11 b/g/n in single stream mode with 20 MHzbandwidth. The advanced algorithms are used to achieve maximum throughput in a real worldcommunication environment with impairments and interference. The PHY implements all the requiredfunctions such as Fast Fourier Transform (FFT), filtering, Forward Error Correction (FEC) that is a Viterbidecoder, frequency, timing acquisition and tracking, channel estimation and equalization, carrier sensing,clear channel assessment and automatic gain control.FeaturesThe IEEE 802.11 PHY supports the following functions:• Single antenna 1x1 stream in 20 MHz channels• Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, and 11 Mbps• Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, and 54 Mbps• Supports IEEE 802.11n HT modulations MCS0-7, 20 MHz, 800 and 400ns guard interval: 6.5, 7.2,13.0, 14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, and 72.2 Mbps• IEEE 802.11n mixed mode operation• Per packet Tx power control• Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recoveryand frame detection8.3  RadioThis section presents information describing the properties and characteristics of the ATWINC3400-MR210CA and Wi-Fi radio transmit and receive performance capabilities of the device.The performance measurements are taken at the RF pin assuming 50Ω impedance; the RF performanceis guaranteed for room temperature of 25oC with a derating of 2-3 dB at boundary conditions.Measurements were taken under typical conditions: VBATT=3.3V; VDDIO=3.3V; temperature: +25ºCTable 8-1. Features and PropertiesFeature DescriptionPart Number ATWINC3400-MR210CAWLAN Standard IEEE 802.11 b/g/n, Wi-Fi compliantHost Interface SPIDimension 22.4 x 14.7 x 2.0 mm ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 28
Feature DescriptionFrequency Range 2.412GHz ~ 2.472GHz (2.4GHz ISM Band)Number of Channels 11 for North America, and 13 for Europe and JapanModulation 802.11b: DQPSK, DBPSK, CCK802.11g/n: OFDM /64-QAM,16-QAM, QPSK, BPSKData Rate 802.11b: 1, 2, 5.5, 11Mbps802.11g: 6, 9, 12, 18, 24, 36, 48, 54MbpsData Rate(20 MHz, normal GI, 800 ns)802.11n: 6.5, 13, 19.5, 26, 39, 52, 58.5, 65MbpsData Rate(20 MHz, short GI, 400 ns)802.11n: 7.2, 14.4, 21.7, 28.9, 43.3, 57.8,65,72.2MbpsOperating temperature -40 to +85oC ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 29
9.  Bluetooth Low Energy 4.0The Bluetooth subsystem implements all the mission critical real-time functions. It encodes/decodes HCIpackets, constructs baseband data packages, manages, and monitors the connection status, slot usage,data flow, routing, segmentation, and buffer control. The Bluetooth subsystem supports Bluetooth LowEnergy modes of operation.Supports the following advanced low energy applications:• Smart energy• Consumer wellness• Home automation• Security• Proximity detection• Entertainment• Sports and Fitness• Automotive ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 30
10.  External Interfaces10.1  Interfacing with the Host MicrocontrollerThis section describes about interfacing the ATWINC3400-MR210CA module with the hostmicrocontroller. The interface comprises of a slave SPI and additional control signals, as shown in thefollowing figure. For more information on SPI interface specification and timing, refer SPI Interface.Additional control signals are connected to the GPIO/IRQ interface of the microcontroller.Figure 10-1. Interfacing with Host MicrocontrollerHost Microcontroller  CHIP_EN RESET WAKE IRQN SPI Wi-Fi ControllerModuleTable 10-1. Host Microcontroller Interface PinsPin Number Function4 RESET_N11 WAKE13 IRQ_N22 CHIP_EN16 SPI_SSN15 SPI_MOSI17 SPI_MISO18 SPI_SCKRelated LinksSPI Interface ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 31
10.2  SPI Interface10.2.1  OverviewThe ATWINC3400-MR210CA has a Serial Peripheral Interface (SPI) that operates as an SPI slave. TheSPI interface can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped asshown in the following table. The SPI is a full-duplex slave-synchronous serial interface that is availableimmediately following reset when pin 10 (SPI_CFG) is tied to VDDIO.Table 10-2. SPI Interface Pin MappingPin # SPI function10 CFG: Must be tied to VDDIO16 SSN: Active Low Slave Select15 MOSI(RXD): Serial Data Receive18 SCK: Serial Clock17 MISO(TXD): Serial Data TransmitWhen the SPI is not selected, that is, when SSN is high, the SPI interface will not interfere with datatransfers between the serial-master and other serial-slave devices. When the serial slave is not selected,its transmitted data output is buffered, resulting in a high impedance drive onto the MISO line.The SPI interface responds to a protocol that allows an external host to read or write any register in thechip as well as initiate DMA transfers.The SPI SSN, MOSI, MISO, and SCK pins of the ATWINC3400-MR210CA have internal programmablepull-up resistors. These resistors should be programmed to be disabled. Otherwise, if any of the SPI pinsare driven to a low level while the ATWINC3400-MR210CA is in the low-power sleep state, the current willflow from the VDDIO supply through the pull-up resistors, increasing the current consumption of themodule.10.2.2  SPI TimingThe SPI Slave interface supports four standard modes as determined by the Clock Polarity (CPOL) andClock Phase (CPHA) settings. These modes are illustrated in the following table and figure.Table 10-3. SPI Slave ModesMode CPOL CPHA0 0 01 0 12 1 03 1 1The red lines in the following figure correspond to Clock Phase = 0 and the blue lines correspond to ClockPhase = 1. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 32
Figure 10-2. SPI Slave Clock Polarity and Clock Phase Timingzz zzSCKCPOL = 0CPOL = 1SSNRXD/TXD(MOSI/MISO)CPHA = 0CPHA = 12 3 4 5 6 7 81 2 3 4 5 6 718The SPI timing is provided in the following figure and table.Figure 10-3. SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0)tLHSCKTXDRXDtWHtHLtWLtODLYtISU tIHDfSCKSSNtSUSSN tHDSSNTable 10-4. SPI Slave Timing Parameters1Parameter Symbol Min. Max. UnitsClock Input Frequency2fSCK — 48 MHzClock Low Pulse Width tWL 4 —nsClock High Pulse Width tWH 5 —Clock Rise Time tLH 0 7Clock Fall Time tHL 0 7TXD Output Delay3tODLY 4 9 from SCK fall12.5 from SCKrise ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 33
Parameter Symbol Min. Max. UnitsRXD Input Setup Time tISU 1 —RXD Input Hold Time tIHD 5 —SSN Input Setup Time tSUSSN 3 —SSN Input Hold Time tHDSSN 5.5 —Note: 1. Timing is applicable to all SPI modes2. Maximum clock frequency specified is limited by the SPI Slave interface internal design, actualmaximum clock frequency can be lower and depends on the specific PCB layout3. Timing based on 15pF output loading10.3  UART InterfaceThe ATWINC3400-MR210CA supports the Universal Asynchronous Receiver/Transmitter (UART)interface. This interface should be used for debug purposes only. The UART is available on pins 14 and19. The UART is compatible with the RS-232 standard, and the ATWINC3400-MR210CA operates asData Terminal Equipment (DTE). It has a two-pin RXD/TXD interface.The default configuration for accessing the UART interface of ATWINC3400-MR210CA is mentionedbelow:• Baud rate: 115200• Data: 8 bit• Parity: None• Stop bit: 1 bit• Flow control: NoneIt also has RX and TX FIFOs, which ensure reliable high-speed reception and low software overheadtransmission. FIFO size is 4 x 8 for both RX and TX direction. The UART also has status registersshowing the number of received characters available in the FIFO and various error conditions, as well theability to generate interrupts based on these status bits.An example of the UART receiving or transmitting a single packet is shown in the following figure. Thisexample shows 7-bit data (0x45), odd parity, and two stop bits.Important:  UART2 supports RTS and CTS flow control. The UART RTS and UART CTSMUST be connected to the host MCU UART and enabled for the UART interface to befunctional.Figure 10-4. Example of UART RX of TX PacketPrevious Packets or Leading Idle BitsCurrent PacketDataStart BitParity Bit Stop BitsNext Packet ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 34
11.  Application Reference DesignThe ATWINC3400-MR210CA module application schematics for different supported host interfaces areshown in this section.11.1  Host Interface - SPIFigure 11-1. ATWINC3400-MR210CA Reference Schematic R5 0R90R3 0R20R8 0TP2R100U1ATWINC3400-MR210I2C_SCL_M  J34I2C_SDA_M  J35RESETN  J7NC1 J3NC2 J4NC3 J5NC4 J6GND5 J36SDIO~_SPI_CFG  J2GND1 J1IRQN  J33UART_TxD J16SPI_MOSI J26SPI_SSN J25SPI_MISO J24SPI_SCK J23UART_RxD J17VBAT  J18CHIP_EN  J19VDDIO  J12GPIO3  J14GPIO4  J15GND3 J22GND4 J28BT_TXD J8BT_RXD J9BT_RTS J10BT_CTS J11 GPIO17  J29GPIO18  J30GPIO19  J31GND2 J13GPIO7  J27GPIO20  J32GND_PAD J49RTC J20R6 0R1 1MR4 0R7 0TP1SPI_SSNSPI_MISOSPI_SCKSPI_MOSIReset_NChip_ENUART_TxDUART_RxDGPIO_17IRQNVBATGPIO_4GPIO_7VDDIOVDDIOTo host U ART  output To host U ART  input  (General Purpose I/O)To host SPI M as ter R esis tors R 2 - R 14 are rec om m ended as placeholders in case filtering of noisy  s ignals is  required. T hey also allow  dis c onnecting of m odule for debug purposes .GPIO_3GPIO_19GPIO_20GPIO_18(T o host GPIO) (T o host GPIO)R12 0R11 0BT_RTSBT_CTSTo Hos t Input To Hos t OutputBT_TxDBT_RxDTo Hos t Input To Hos t OutputR14 0R13 0C10.1uFU2 32.768KHzOE  3VSS 2O  1VDD  4VDDIO Note:  It is recommended to add test points for module pins J8, J9, J10, J11, J16 and J17 in the design.The following table provides the reference Bill of Material (BoM) details for the ATWINC3400-MR210CAmodule with SPI as host interface.Table 11-1. ATWINC3400-MR210CA Reference Bill of Materials for SPI OperationItem Quantity ReferenceValue Description Manufacturer PartNumberFootprint1 1 U1 ATWINC3400-MR210CAWi-Fi/Bluetooth/BLEMicrochipTechnologyInc.®ATWINC3400-MR210CACustom ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 35
Item Quantity ReferenceValue Description Manufacturer PartNumberFootprintComboModule2 1 U2 ASH7KW-32.768kHZ-L-TOscillator,32.768 kHz,+0/-175 ppm,1.2V - 5.5V,-40°C - +85°CAbracon®CorporationASH7KW-32.768kHZ-L-TOSCCC320X150X100-4N3 1 R1 1M RESISTOR,Thick Film, 1MOhm, 0201Panasonic ERJ-1GEJ105CRS02014 13 R2-R14 0 RESISTOR,Thick Film, 0Ohm, 0201Panasonic ERJ-1GN0R00CRS0201 ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 36
12.  Module Outline DrawingsThe ATWINC3400-MR210CA module package details are outlined in the following figure.Figure 12-1.  ATWINC3400-MR210CA Footprint and Module Package Drawings - Top , Bottom andSide ViewATWINC3400-MR210CAATWINC3400-MR210CAUntoleranced dimensionsNote: 1. Dimensions are in mm.2. It is recommended to have a 5x5 grid of GND vias solidly connecting the exposed GND paddle ofthe module to the ground plane on the inner/other layers of the host board. This will provide a goodground and thermal transfer for the ATWINC3400-MR210CA module. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 37
13.  Design ConsiderationThis section provides the guidelines on module placement and routing to achieve the best performance.13.1  Module Placement and Routing GuidelinesIt is critical to follow the recommendations listed below to achieve the best RF performance:• The module must be placed on the host board and the chip antenna area must not overlap with thehost board. The following figure on placement reference shows the best, poor, and worst casemodule placements in the host board.Figure 13-1. ATWINC3400-MR210CA Placement ExampleCaution:  Do not place the module in the middle of the host board or far away from thehost board edge.• Follow the host board mechanical recommendation, ground plane and keep out recommendationsas shown in the following figure. Module chip antenna is specifically tuned for this host boardmechanical recommendation as shown in the following figure. The host PCB should have athickness of 1.5 mm– Follow the module placement and keep out recommendation as shown in the following figure• Avoid routing any traces on the top layer of the host board which will be directly belowthe module area.• In keep out region, there should be no copper traces in all signal layers.• Avoid placing any components (like mechanical spacers, bumpon and so on) on thehost board closer to the chip antenna region. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 38
• Place GND polygon pour below the module on the top layer of the host board. Avoidbreaks in this GND plane, ensure continuous GND plane for better RF performance.• GND polygon pour in the top layer of the host board should have a minimum area of 20x 40 mm.• Place sufficient GND vias on host board edge and below the module for better RFperformance.• It is recommended to have a 5x5 grid of GND vias solidly connecting the exposed GNDpaddle of the module to the ground plane of the host board. This will act as a goodground and thermal conduction path for the ATWINC3400-MR210CA module. The GNDvias should have a minimum via hole size of 0.2 mm.• Antenna on the module should not be placed in direct contact or close proximity toplastic casing/objects. Keep a minimum clearance of >7 mm in all directions around thechip antenna.Figure 13-2. ATWINC3400-MR210CA Placement Reference13.2  Antenna PerformanceThe ATWINC3400-MR210CA uses a chip antenna which is fed via matching network. The table belowlists the technical specification of the chip antenna.Table 13-1. Chip antenna specificationParamater ValuePeak gain 0.5 dBiOperating frequency 2400 - 2500 MHz ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 39
Paramater ValueAntenna P/N 2450AT18A100Antenna vendor Johanson Technology ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 40
14.  Reflow Profile InformationThis section provides the guidelines for the reflow process to get the module soldered to the customer'sdesign.14.1  Storage Condition14.1.1  Moisture Barrier Bag Before OpeningA moisture barrier bag must be stored at a temperature of less than 30°C with humidity under 85% RH.The calculated shelf life for the dry-packed product is 12 months from the date the bag is sealed.14.1.2  Moisture Barrier Bag OpenHumidity indicator cards must be blue, < 30%.14.2  Solder PasteThe SnAgCu eutectic solder with melting temperature of 217°C is most commonly used for lead-freesolder reflow application. This alloy is widely accepted in the semiconductor industry due to its low cost,relatively low melting temperature, and good thermal fatigue resistance. Some recommended pastesinclude NC-SMQ® 230 flux and Indalloy® 241 solder paste made up of 95.5 Sn/3.8 Ag/0.7 Cu or SENJUN705-GRN3360-K2-V Type 3, no clean paste.14.3  Stencil DesignThe recommended stencil is laser-cut, stainless-steel type with thickness of 100 µm to 130 µm andapproximately a 1:1 ratio of stencil opening to pad dimension. To improve paste release, a positive taperwith bottom opening 25 µm larger than the top is utilized. Local manufacturing experience may find othercombinations of stencil thickness and aperture size to get good results.14.4  Baking ConditionsThis module is rated at MSL level 3. After the sealed bag is opened, no baking is required within 168hours as long as the devices are held at ≤ 30°C/60% RH or stored at < 10% RH.The module requires baking before mounting if:• The sealed bag has been open for more than 168 hours• The humidity indicator card reads more than 10%• SIPs need to be baked for eight hours at 125°C14.5  Soldering and Reflow ConditionOptimization of the reflow process is the most critical factor considered for lead-free soldering. Thedevelopment of an optimal profile must account the paste characteristics, the size of the board, thedensity of the components, the mix of the larger and smaller components, and the peak temperaturerequirements of the components. An optimized reflow process is the key to ensuring a successful lead-free assembly and achieves high yield and long-term solder joint reliability. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 41
Temperature ProfilingTemperature profiling must be performed for all new board designs by attaching thermocouples at thesolder joints, on the top surface of the larger components, and at multiple locations of the boards. This isto ensure that all components are heated to a temperature above the minimum reflow temperatures andthe smaller components do not exceed the maximum temperature limit. The SnAgCu solder alloy melts at~217°C, so the reflow temperature peak at joint level must be 15 to 20°C higher than meltingtemperature. The targeted solder joint temperature for the SnAgCu solder must be ~235°C. For larger orsophisticated boards with a large mix of components, it is also important to ensure that the temperaturedifference across the board is less than 10 degrees to minimize board warpage. The maximumtemperature at the component body must not exceed the MSL3 qualification specification.14.5.1  Reflow OvenIt is strongly recommended that a reflow oven equipped with more heating zones and Nitrogenatmosphere must be used for the lead-free assembly. The Nitrogen atmosphere is shown to improve thewet-ability and reduce temperature gradient across the board. It can also enhance the appearance of thesolder joints by reducing the effects of oxidation.The following items must also be observed in the reflow process:1. Some recommended pastes include:– NC-SMQ® 230 flux and Indalloy® 241 solder paste made up of 95.5 Sn/3.8 Ag/0.7 Cu– SENJU N705-GRN3360-K2-V Type 3, no clean paste2. Allowable reflow soldering iterations:– Three times based on the following reflow soldering profile (see, following figure).3. Temperature profile:– Reflow soldering must be done according to the following temperature profile (see, followingfigure).– Peak temperature: 250°C ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 42
Figure 14-1. Solder Reflow ProfileCleaningThe exposed ground paddle helps to self-align the module, avoiding pad misalignment. The use of noclean solder pastes is recommended. As a result of reflow process, ensure to completely dry the no-cleanpaste fluxes. This may require longer reflow profiles and/or peak temperatures toward the high end of theprocess window as recommended by the solder paste vendor. It is believed that uncured flux residuescan lead to corrosion and/or shorting in accelerated testing and possibly the field.ReworkThe rework removes the mounted SIP package and replaces it with a new unit. It is recommended thatonce an ATWINC3400-MR210CA module is removed and it must never be reused. During the reworkprocess, the mounted module and PCB are heated partially, and the module is removed. It isrecommended to heat-proof the proximity of the mounted parts and junctions and use the best nozzle forrework that is suited to the module size. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 43
15.  Module Assembly ConsiderationsThe ATWINC3400-MR210CA module is assembled with an EMI shield to ensure compliance with EMIemission and immunity rules. The EMI shield is made of a tin-plated steel (SPTE) and is not hermeticallysealed. Solutions such as IPA and similar solvents can be used to clean this module. Cleaning solutionscontaining acid must never be used on the module.The ATWINC3400-MR210CA module is manufactured without any conformal coating applied. It is thecustomer's responsibility if a conformal coating is specified and/or applied to this module. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 44
16.  Regulatory ApprovalRegulatory Approvals received for ATWINC3400-MR210CA:• United States/FCC ID: 2ADHKWINC3400• Canada/ISED:– IC: 20266-ATWINC3400– HVIN: ATWINC3400-MR210CA• Europe - CE (Approval pending)16.1  United StatesThe ATWINC3400-MR210CA module has received Federal Communications Commission (FCC) CFR47Telecommunications, Part 15 Subpart C “Intentional Radiators” single-modular approval in accordancewith Part 15.212 Modular Transmitter approval. Single-modular transmitter approval is defined as acomplete RF transmission sub-assembly, designed to be incorporated into another device, that mustdemonstrate compliance with FCC rules and policies independent of any host. A transmitter with amodular grant can be installed in different end-use products (referred to as a host, host product, or hostdevice) by the grantee or other equipment manufacturer, then the host product may not require additionaltesting or equipment authorization for the transmitter function provided by that specific module or limitedmodule device.The user must comply with all of the instructions provided by the Grantee, which indicate installationand/or operating conditions necessary for compliance.A host product itself is required to comply with all other applicable FCC equipment authorizationregulations, requirements, and equipment functions that are not associated with the transmitter moduleportion. For example, compliance must be demonstrated: to regulations for other transmitter componentswithin a host product; to requirements for unintentional radiators (Part 15 Subpart B), such as digitaldevices, computer peripherals, radio receivers, etc.; and to additional authorization requirements for thenon-transmitter functions on the transmitter module (i.e., Verification or Declaration of Conformity) asappropriate (e.g., Bluetooth and Wi-Fi transmitter modules may also contain digital logic functions).16.1.1  Labeling And User Information RequirementsThe ATWINC3400-MR210CA module has been labeled with its own FCC ID number, and if the FCC ID isnot visible when the module is installed inside another device, then the outside of the finished product intowhich the module is installed must display a label referring to the enclosed module. This exterior labelcan use wording as follows:For the ATWINC3400-MR210CA:Contains Transmitter Module FCC ID: 2ADHKWINC3400orContains FCC ID: 2ADHKWINC3400This device complies with Part 15 of the FCC Rules. Operation is subject to the following twoconditions: (1) this device may not cause harmful interference, and (2) this device must acceptany interference received, including interference that may cause undesired operationA user's manual for the finished product should include the following statement: ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 45
This equipment has been tested and found to comply with the limits for a Class B digital device,pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protectionagainst harmful interference in a residential installation. This equipment generates, uses and can radiateradio frequency energy, and if not installed and used in accordance with the instructions, may causeharmful interference to radio communications. However, there is no guarantee that interference will notoccur in a particular installation. If this equipment does cause harmful interference to radio or televisionreception, which can be determined by turning the equipment off and on, the user is encouraged to tryto correct the interference by one or more of the following measures:• Reorient or relocate the receiving antenna• Increase the separation between the equipment and receiver• Connect the equipment into an outlet on a circuit different from that to which the receiver isconnected• Consult the dealer or an experienced radio/TV technician for helpAdditional information on labeling and user information requirements for Part 15 devices can be found inKDB Publication 784748, which is available at the FCC Office of Engineering and Technology (OET)Laboratory Division Knowledge Database (KDB) https://apps.fcc.gov/oetcf/kdb/index.cfm16.1.2  RF ExposureAll transmitters regulated by FCC must comply with RF exposure requirements. KDB 447498 General RFExposure Guidance provides guidance in determining whether proposed or existing transmitting facilities,operations or devices comply with limits for human exposure to Radio Frequency (RF) fields adopted bythe Federal Communications Commission (FCC).From the FCC Grant: Output power listed is conducted. This transmitter is restricted for use with thespecific antenna(s) tested in this application for Certification.The antenna(s) used with this transmitter must be installed to provide a separation distance of at least 6.5cm from all persons and must not be co-located or operating in conjunction with any other antenna ortransmitter. Users and installers must be provided with antenna installation instructions and transmitteroperating conditions for satisfying RF exposure compliance.16.1.3  Helpful Web SitesFederal Communications Commission (FCC): http://www.fcc.govFCC Office of Engineering and Technology (OET) Laboratory Division Knowledge Database (KDB): https://apps.fcc.gov/oetcf/kdb/index.cfm16.2  CanadaThe ATWINC3400-MR210CA module has been certified for use in Canada under Innovation, Science andEconomic Development Canada (ISED, formerly Industry Canada) Radio Standards Procedure (RSP)RSP-100, Radio Standards Specification (RSS) RSS-Gen and RSS-247. Modular approval permits theinstallation of a module in a host device without the need to recertify the device.16.2.1  Labeling and User Information RequirementsLabel Requirements (from RSP-100 Issue 11, Section 3): The host device shall be properly labeled toidentify the module within the host device.The Innovation, Science and Economic Development Canada certification label of a module shall beclearly visible at all times when installed in the host device; otherwise, the host product must be labeled to ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 46
display the Innovation, Science and Economic Development Canada certification number of the module,preceded by the word “Contains” or similar wording expressing the same meaning, as follows:For the ATWINC3400-MR210CA:Contains IC: 20266-ATWINC3400User Manual Notice for License-Exempt Radio Apparatus (from Section 8.4 RSS-Gen, Issue 4,November 2014): User manuals for license-exempt radio apparatus shall contain the following orequivalent notice in a conspicuous location in the user manual or alternatively on the device or both:This device complies with Industry Canada license exempt RSS standard(s). Operation issubject to the following two conditions:(1) This device may not cause interference, and(2) This device must accept any interference, including interference that may cause undesiredoperation of the device.Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radioexempts de licence. L'exploitation est autorisée aux deux conditions suivantes:(1) l'appareil ne doit pas produire de brouillage, et(2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si lebrouillage est susceptible d'en compromettre le fonctionnement.Guidelines on Transmitter Antenna for License Exempt Radio Apparatus:Under Industry Canada regulations, this radio transmitter may only operate using an antenna ofa type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reducepotential radio interference to other users, the antenna type and its gain should be so chosenthat the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary forsuccessful communication.Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peutfonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pourl'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectriqueà l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que lapuissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire àl'établisse-ment d'une communication satisfaisante.16.2.2  RF ExposureAll transmitters regulated by Innovation, Science and Economic Development Canada (ISED) mustcomply with RF exposure requirements listed in RSS-102 - Radio Frequency (RF) Exposure Complianceof Radio communication Apparatus (All Frequency Bands).This transmitter is restricted for use with a specific antenna tested in this application for certification, andmust not be co-located or operating in conjunction with any other antenna or transmitters within a hostdevice, except in accordance with Canada multi-transmitter product procedures.The installation of the transmitter must ensure that the antenna has a separation distance of at least 6.5cm from all persons or compliance must be demonstrated according to the ISED SAR procedures.16.2.3  Helpful Web SitesInnovation, Science and Economic Development Canada: http://www.ic.gc.ca/ ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 47
16.3  EuropeNote:  Pending for an approval.The ATWINC3400-MR210CA module is a Radio Equipment Directive (RED) assessed radio module thatis CE marked and has been manufactured and tested with the intention of being integrated into a finalproduct.The ATWINC3400-MR210CA module has been tested to RED 2014/53/EU Essential Requirements forHealth and Safety (Article (3.1(a)), Electromagnetic Compatibility (EMC) (Article 3.1(b)), and Radio(Article 3.2), which is summarized in the following European Compliance Testing table.The ETSI provides guidance on modular devices in the “Guide to the application of harmonised standardscovering articles 3.1b and 3.2 of the RED 2014/53/EU (RED) to multi-radio and combined radio and non-radio equipment” document available at http://www.etsi.org/deliver/etsi_eg/203300_203399/203367/01.01.01_60/eg_203367v010101p.pdf.Note:  To maintain conformance to the testing listed in the following European Compliance Testing tablethe module shall be installed in accordance with the installation instructions in this data sheet and shallnot be modified. When integrating a radio module into a completed product, the integrator becomes themanufacturer of the final product and is therefore responsible for demonstrating compliance of the finalproduct with the essential requirements against the RED.16.3.1  Labeling and User Information RequirementsThe label on the final product that contains the ATWINC3400-MR210CA module must follow CE markingrequirements.Table 16-1. European Compliance TestingCertification Standards Article LaboratoryReportNumberDateSafety EN60950-1:2006/A11:2009/A1:2010/A12:2011/A2:2013[3.1.(a)]TUVRheinland,Taiwan10062655 001 30-Oct-2017Health EN300328 V2.1.1/EN62311:2008 50103733 00150103734 00130-Oct-2017EMC EN301489-1 V2.1.1EN301489-1 V2.2.0[3.1(b)] 10062417 001 30-Oct-2017EN301489-17 V3.1.1EN301489-17 V3.2.0Radio EN300328 V2.1.1 [3.2] 50103733 00150103734 00130-Oct-201716.3.2  Conformity AssessmentFrom ETSI Guidance Note EG 203367, section 6.1, when non-radio products are combined with a radioproduct:If the manufacturer of the combined equipment installs the radio product in a host non-radio product inequivalent assessment conditions (i.e. host equivalent to the one used for the assessment of the radioproduct) and according to the installation instructions for the radio product, then no additional assessmentof the combined equipment against article 3.2 of the RED is required. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 48
The European Compliance Testing listed in the preceeding table was performed using the integral chipantenna.16.3.2.1  Simplified EU Declaration of ConformityHereby, Microchip Technology Inc. declares that the radio equipment type ATWINC3400-MR210CA is incompliance with Directive 2014/53/EU.The full text of the EU declaration of conformity for this product is available at http://www.microchip.com/design-centers/wireless-connectivity/.16.3.3  Helpful WebsitesA document that can be used as a starting point in understanding the use of Short Range Devices (SRD)in Europe is the European Radio Communications Committee (ERC) Recommendation 70-03 E, whichcan be downloaded from the European Communications Committee (ECC) at: http://www.ecodocdb.dk/.Additional helpful web sites are:• Radio Equipment Directive (2014/53/EU):https://ec.europa.eu/growth/single-market/european-standards/harmonised-standards/rtte_en• European Conference of Postal and Telecommunications Administrations (CEPT):http://www.cept.org• European Telecommunications Standards Institute (ETSI):http://www.etsi.org• The Radio Equipment Directive Compliance Association (REDCA):http://www.redca.eu/16.4  Other Regulatory Information• For information about other countries' jurisdictions not covered here, refer to http://www.microchip.com/ design-centers/wireless-connectivity• Should other regulatory jurisdiction certification be required by the customer, or the customer needsto recertify the module for other reasons, contact Microchip for the required utilities anddocumentation ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 49
17.  Reference DocumentationThe following are the set of collaterals to ease integration and device ramp.• Wi-Fi Network Controller Software Design Guide Application Note• Integrated Serial Flash Memory Download Procedure Application Note• Wi-Fi Network Controller Software Programming Guide Application Note• ATWINC3400 XPro User Guide• BLE Example Profiles Applications User GuideNote: For a complete listing of development-support tools and documentation, visit http://www.microchip.com/wwwproducts/en/ATWINC3400 or refer to the customer support section on options to the nearestMicrochip field representative. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 50
18.  Document Revision HistoryRev A - 10/2017Section ChangesDocument Initial Release ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 51
The Microchip Web SiteMicrochip provides online support via our web site at http://www.microchip.com/. This web site is used asa means to make files and information easily available to customers. Accessible by using your favoriteInternet browser, the web site contains the following information:•Product Support – Data sheets and errata, application notes and sample programs, designresources, user’s guides and hardware support documents, latest software releases and archivedsoftware•General Technical Support – Frequently Asked Questions (FAQ), technical support requests,online discussion groups, Microchip consultant program member listing•Business of Microchip – Product selector and ordering guides, latest Microchip press releases,listing of seminars and events, listings of Microchip sales offices, distributors and factoryrepresentativesCustomer Change Notification ServiceMicrochip’s customer notification service helps keep customers current on Microchip products.Subscribers will receive e-mail notification whenever there are changes, updates, revisions or erratarelated to a specified product family or development tool of interest.To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on“Customer Change Notification” and follow the registration instructions.Customer SupportUsers of Microchip products can receive assistance through several channels:• Distributor or Representative• Local Sales Office• Field Application Engineer (FAE)• Technical SupportCustomers should contact their distributor, representative or Field Application Engineer (FAE) for support.Local sales offices are also available to help customers. A listing of sales offices and locations is includedin the back of this document.Technical support is available through the web site at: http://www.microchip.com/support ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 52
Product Identification SystemTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.Microchip Devices Code Protection FeatureNote the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.• Microchip believes that its family of products is one of the most secure families of its kind on themarket today, when used in the intended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All ofthese methods, to our knowledge, require using the Microchip products in a manner outside theoperating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so isengaged in theft of intellectual property.• Microchip is willing to work with the customer who is concerned about the integrity of their code.• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of theircode. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving thecode protection features of our products. Attempts to break Microchip’s code protection feature may be aviolation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your softwareor other copyrighted work, you may have a right to sue for relief under that Act.Legal NoticeInformation contained in this publication regarding device applications and the like is provided only foryour convenience and may be superseded by updates. It is your responsibility to ensure that yourapplication meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORYOR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITSCONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in lifesupport and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resultingfrom such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectualproperty rights unless otherwise stated.TrademarksThe Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings,BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA,SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks ofMicrochip Technology Incorporated in the U.S.A. and other countries. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 53
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLightLoad, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of MicrochipTechnology Incorporated in the U.S.A.Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController,dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit SerialProgramming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi,motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, OmniscientCode Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REALICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, TotalEndurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA aretrademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary ofMicrochip Technology Inc., in other countries.All other trademarks mentioned herein are property of their respective companies.© 2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.ISBN:Quality Management System Certified by DNVISO/TS 16949Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and waferfabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC®DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchip’s quality system for the design and manufacture of developmentsystems is ISO 9001:2000 certified. ATWINC3400-MR210CA© 2017 Microchip Technology Inc.  Draft Datasheet Preliminary DS00000000A-page 54
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