HARRIS TR-0017-E Sitepro Base Station User Manual RX Synth

HARRIS CORPORATION Sitepro Base Station RX Synth

RX Synth

Maintenance ManualLBI-38641FVHF RECEIVER SYNTHESIZER MODULE19D902781G1 & G2DESCRIPTIONThe Receiver Synthesizer Module provides the localoscillator signal (LO) to the Receiver Front End Moduleof the MASTR III base station. The module also providesthe reference oscillator signal to the transmitter synthe-sizer. Receiver Synthesizer Module 19D902781G1(Group 1) generates an output injection signal in the 157to 172 MHz range, and 19D902781G2 (Group 2) gener-ates a signal in the 129 to 152 MHz Range.The Receiver Synthesizer Module is a phase-lockedloop (PLL) design, as shown in the block diagram (Figure1). Its output is generated directly by the VCO Q1 andbuffered by Monolithic Microwave Integrated Circuits(MMIC) U1 and U3.The logic signals from controller (U10, 12, and 13)determine the synthesizer frequency. Frequency stabilityis maintained by either using the internal reference oscil-lator Y1 or by applying a high precision reference signalto the EXT Reference Oscillator Port J4. The internalreference oscillator is a temperature controlled crystaloscillator (TCXO) operating at 12.8 MHz. The oscillatorhas a stability of ±1.5 ppm over the temperature range of-30°C to +75°C. See the table containing General Speci-fications for the minimum external oscillator specifica-tions.The buffered VCO output is sampled by the resistivesplitter and conditioned by buffer amplifier U2. It is thenfed to the divide by 64/65 dual modulus prescaler U5. Thedivided output from the prescaler is connected to the Fininput of the PLL U6. Within the PLL the divided VCOinput signal Fin is divided again. The PLL also dividesdown the 12.8 MHz reference signal. Three inputs fromthe controller; ENABLE, CLOCK, and serial DATA pro-gram the PLL divider circuits.TABLE OF CONTENTSPageDESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Front CoverGENERAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1CIRCUIT ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2VOLTAGE CONTROLLED OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2BUFFER AMPLIFIERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2REFERENCE OSCILLATOR AND BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . 2PRESCALER AND SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2LOOP FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2DIGITAL CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2VOLTAGE REGULATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2MAINTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3TEST AND ALIGNMENT PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3TROUBLESHOOTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ASSEMBLY DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4OUTLINE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5SCHEMATIC DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12PRODUCTION CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13IC DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13M/A-COM Wireless Systems3315 Old Forest RoadLynchburg, Virginia 24501(Outside USA, 434-385-2400) Toll Free 800-528-7711www.macom-wireless.com Printed in U.S.A.
The divided reference signal and the divided VCO signalare compared in the PLL phase detector. When the referenceand VCO signals are identical the PLL phase detector generatesa constant DC output voltage. This voltage is buffered by U8and filtered by the loop filter circuit. It is then applied to Q1setting the VCO on frequency.If the compared frequencies (phases) differ, an error voltageis generated which adjusts the VCO frequency. During thisout-of-lock condition, the PLL also sends a Lock Detect signal(LD) to the controller and lights the FAULT LED on the frontpanel of the module.CIRCUIT ANALYSISThe Receiver Synthesizer Module consists of the follow-ing circuits:•Voltage Controlled Oscillator•Buffer Amplifiers•Reference Oscillator and Buffer•Prescaler and Synthesizer•Loop Filter•Digital Control•Voltage RegulatorsVOLTAGE CONTROLLED OSCILLATORThe free running Voltage Controlled Oscillator (VCO) iscomposed of a grounded-gate JFET (Q1) and associatedcircuitry. Inductor L10 and associated capacitors form theresonant tank circuit. The circuit’s use of high-Q componentsminimizes phase noise.Frequency tuning of the VCO is done by changing theDC output voltage level from the loop filter U14. The LoopFilter Out signal from U14 is routed through L4 and R3 andapplied to the two varicap diodes D4 and D5. The voltagelevel applied determines the diodes’ capacitance and sets theresonant frequency of the oscillator. If the VCO drifts or thefrequency is changed, the DC voltage level changes causingthe VCO’s resonant frequency to change. The output of theoscillator is then applied to a buffer amplifier. Course adjust-ment of frequency is done by adjusting trimmer capacitorC52 while applying a calibration voltage to the V_TUNEline connected to U14.4-11.BUFFER AMPLIFIERSThe MMIC Buffer Amplifier stage is composed of threeMMICs (U1, U2, and U3) and a resistive splitter. The ampli-fiers serve two purposes; amplifying the local oscillatorsignal (LO OUTPUT) for injection into the Receiver FrontEnd assembly and providing a feedback signal to the synthe-sizer Phase-Locked Loop (PLL).Copyright© 1992-2002, M/A-COM Private Radio Systems, Inc. All rights reserved.TABLE 1 - GENERAL SPECIFICATIONSITEM SPECIFICATIONFREQUENCY TUNINGOutput Injection Signal INJECTION FREQ. FREQ. BAND157.4 MHz - 172.2 MHz (G1) 136 MHz - 150.8 MHz129.4 MHz - 152.6 MHz (G2) 150.8 MHz - 174 MHzElectricalFull SpecificationsDegraded SpecificationsChannel Spacing2 MHz3 MHz5 kHzFREQUENCY STABILITY ±1.5 ppmLO POWER OUTPUT 1.5 dBm ±1.5 dBmLO NOMINAL IMPEDANCE 50 OhmsPHASE NOISE@ 25 kHz Offset@ 30 kHz Offset -142 dBc/Hz-147 dBc/HzHUM AND NOISECompanion Receiver -60 dBHARMONICS @ LO PORT <-30 dBcSWITCHING SPEED < 50 msCURRENT DRAIN+13.8V+12V<200 mA<50 mAREFERENCE OSCILLATORFrequency OutputPower OutputImpedance12.8 MHz ±1.5 ppm0 dBm ±1.5 dBm50 ohmsEXT. REFERENCE OSCILLATORFrequency OutputPower OutputImpedance5.00 MHz to 17.925 MHz (must be divisible by thechannel spacing)10 dBm ±3 dBm into 50 ohms50 ohmsFigure 1 - Receiver Synthesizer Block DiagramLBI-38641F1
Integrated circuits U1 and U3 provide amplification ofthe local oscillator signal. The output of U1 is fed to aresistive signal splitter composed of R13 through R18. Oneof the resistive signal splitter outputs drives amplifier U3.The U3 output signal is coupled by C17 to a low-pass filternetwork (C24 and C25, L6, L8, and L9) and a resistive pad(R25, R26 and R30) for isolation. The local oscillator signalis finally routed to J2, LO OUT, for connection to theReceiver Front End Assembly. The LO output level at BNCconnector J2 is nominally 0 dBm.The other output of the resistive signal splitter drives U2.The amplified output from U2, PRESCALER BUFFEROUT, is coupled to the 50 ohm input of the prescaler U5 viacapacitors C16 and C45.REFERENCE OSCILLATOR AND BUFFERThe reference oscillator section provides a referencesignal to the PLL section. The circuit design allows usingeither an external or internal oscillator.When using an external oscillator, the internal oscillatoris disabled by placing a logic low on the INT OSC line fromthe T/R Shelf Interface Board. A high precision externaloscillator may then be connected to the module through theexternal reference oscillator connector J4, EXT REF IN. J4has a 50 ohm input impedance and is coupled to the base ofQ12. Buffer Q12 conditions the signal and applies it to thesynthesizer U6 via coupling capacitor C10.The internal reference oscillator, Y1, provides a 12.8MHz signal with a stability of ±1.5 ppm. It is enabled byapplying a logic high signal on the INT OSC line. This signalturns on Q2, allowing it to conduct and apply +5 volts to pin1 of the oscillator Y1. The 12.8 MHz output signal (Y1 pin2) is then sent to the synthesizer via coupling capacitor C9.The reference oscillator signal, either external or inter-nal, is also routed to Q13 via coupling capacitor C54. Theoutput taken from the emitter of Q13 is applied through C11to the input of Buffer Amplifier U4. The buffered signal iscoupled through C12 to a low pass filter network(C32,C33,C34, and L7) and a resistive pad (R27, R28, andR31) for isolation. The output from the resistive pad is thenconnected to J3, REF OUT, making the reference oscillatorsignal available for external use.PRESCALER AND SYNTHESIZER ICThe integrated circuit U6 is the heart of the synthesizer.It contains the necessary frequency dividers and controlcircuitry to synthesize output frequencies by the techniqueof dual modulus prescaling. U6 also contains an analogsample and hold phase detector and a lock detector circuit.Within the U6 are three programmable dividers whichare serially loaded using the CLOCK, DATA, and ENABLEinputs (pins 11, 12, and 13 respectively). A serial data stream(DATA) on pin 12 is shifted into the internal shift registersby low to high transitions on the clock input (CLOCK) at pin11. A logic high (ENABLE) on pin 13 then transfers theprogram information from the shift registers to the dividerlatches. The serial data determines the VCO frequency bysetting the internal R, A, and N dividers.The 12.8 MHz reference oscillator signal OSCIN is in-ternally routed to the "R" divider. The "R" divider dividesdown the 12.8 MHz reference signal to a lower frequency,Fr, as directed by the input data and applies the signal to theinternal analog phase and lock detectors.The "A" and "N" dividers process the loop feedbacksignal from the VCO (by way of the dual modulus prescalerU5). The output of the "N" divider, Fv, is a divided downversion of the VCO output frequency. This signal is alsoapplied to the internal phase detector. The ramp and holdconstants are determined by C26, R37, C31, and R36.The analog phase detector output voltage (PD OUT) isproportional to the phase difference between Fv and Fr. Thisoutput serves as the loop error signal. When operating on thecorrect frequency, the inputs to the phase detector are iden-tical and the output voltage of the analog phase detector isconstant. If the compared frequencies (phases) differ, theanalog phase detector increases or decreases the DC outputvoltage (PD OUT). This error signal voltage tunes the VCOto whatever frequency is required to keep Fv and Fr locked(in phase).The lock detector furnishes the Fault circuit in U13 withthe lock detect (LD) signal. When Fv and Fr are in phase, thelock detector output sends a logic high on the LD line to thefault circuit U13. If the VCO is not locked onto the correctfrequency, the resulting out-of-phase condition causes theoutput from the lock detector to be a logic low.LOOP FILTERThe error signal, ANOUT, is applied to the loop filter atU8.2-5 and U8.1-3. U8.2 acts as a buffer amplifier with gain.The output signal from the amplifier is applied to a loop filterconsisting of R42, R43, R44, C35 and C36 via the bilateralswitch U14. The filter removes noise and sampling frequen-cies from the error voltage. The switch, U14, selects theproper filter configuration for operation in the narrow band,wide band or tuning mode. The control signals(OPEN_LOOP, ENABLE_NOT, and TUNE_CTRL) forU14 are derived from the digital control circuits U10, U12, andU13. U8.1 provides a buffered output for testing at the DINconnector on the rear of the module.DIGITAL CONTROLLogic control circuits (other than those inside the synthe-sizer IC - U6) consist of the following:•Digital Control Circuit (U10, U12, & U13)•Level Shifters•Fault CircuitThe Digital Control Circuits U10, U12, & U13 serve as aninterface between the controller and the synthesizer IC.As an address decoder, U10 enables the input gates whenthe A0, A1, and A2 input lines (pins 4, 3, and 2) receive thecorrect address code from the controller. For the Receiversynthesizer the enable address is 010 on A0, A1, and A2respectively. After receiving the proper logic code, the inputgate U12 is enabled. This allows the ENABLE, CLOCK, andserial DATA information to pass on to the synthesizer via thelevel shifters.The Level Shifters Q3, Q4, and Q5 convert the five (5) voltlogic level to the eight (8) volt logic level required by thesynthesizer.The Fault circuit, U13, monitors the lock detect signal fromthe PLL synthesizer. Under normal (locked) condition, the PLLsends a logic high signal to U13. U13 processes the signal andproviding a logic high output which saturates Q6. With Q6saturated, the FAULT LED (CR1) turns off. U13 also sends alogic high signal, FLAG 2, (U13.3-8) to the controller indicat-ing the VCO’s frequency is correct.When the VCO is not on the correct frequency, the synthe-sizer sends a logic low signal to U13. This causes U13 to cutoffQ6 which turns on the FAULT LED. U13 also sends a logiclow signal to the controller indicating the VCO’s frequency isincorrect.VOLTAGE REGULATORSVoltage regulators U15 and U16 reduce the +13.8 VF lineto +5 Vdc and +8 Vdc respectively. The output from U15(+5V_SYN) is used by both the synthesizer and logic circuitrywhile the 8 Vdc output from U16 is used for the op-amps, levelshifters, and the discrete +8V OSC regulator circuit.The discrete +8V OSC regulator circuit is a linear regulatorconsisting of U9A, Q7, Q8, and associated circuitry. The erroramplifier U9A controls Q7 and pass element Q8. The +8V OSCis used as the power source for the VCO circuit, where addi-tional filtering is provided to keep noise to a minimumMAINTENANCERECOMMENDED TEST EQUIPMENTThe following test equipment is required to test the Synthe-sizer Module:1. Modulation Analyzer; HP 8901A, or equivalent2. Power Supply; 12.0 Vdc @ 500 mA3. Frequency Counter; 10 MHz - 250 MHz4. Power Meter; -20 dBm to +10 dBm5. Spectrum Analyzer; 0 - 1 GHzTEST AND ALIGNMENTInitializationApply +12 Vdc to the test fixture.Current consumptionMeasure the current through pins 15A,15B, 15C, 16A, 16B,and 16C. Verify the current is less than 250 mA. Total currentis the +13.8 VF current and +12 Vdc current com-bined.Reference OscillatorAdjust Y1 for an output frequency of 12.8 MHz ±5 Hz.Measure the output power of the reference oscillator output(J3).Verify the output power is 0 dBm ±1.5 dBm.Oscillator AlignmentGround the ENABLE TEST line (pin 22A). Apply +5 Vdcto the V_TUNE line (pin 26A). Measure the frequency of thefree running oscillator at the LO OUT port (J2).LBI-38641F2
Adjust the trimmer capacitor C52 to the correct frequency:Group 1 - 170 MHz ±100 kHz.Group 2 - 150 MHz ±100 kHz.Synthesizer LoadingUnground the ENABLE TEST line (pin 22A). Load thesynthesizer IC Group 1 - 170 MHz.Group 2 - 150 MHz.Verify the lock indicator (CR1) is off or the FLAG 2 line ishigh.Hum and NoiseInitialize the HP 8901A for 300 Hz - 3 kHz, 750 us deem-phasis, average FM deviation, and 0.44 dB reference for thedeviation.Verify the hum and noise (J2) is less than -55 dB.Output Power and Harmonic ContentVerify the output power (J2) at the fundamental frequencyis:0 dBm ±2.0 dBVerify the harmonic content is less than -30dBc.ContinuedThe following service information applies whenaligning, testing, or troubleshooting the RX Synthe-sizer:•Logic Levels:Logic 1 = high = 4.5 to 5.5 VdcLogic 0 = Low = 0 to 0.5 Vdc•Receiver Synthesizer Address = A0 A1 A2 = 010•Synthesizer data input stream is as follows:14-bit "R" divider most significant bit (MSB) = R13 through "R" divider least significant bit (LSB) = R010-bit "N" divider MSB = N9 through "N" divider LSB = N07-bit "A" divider MSB = A6 through "A" dividerLSB = A0Single high Control bit (last bit)Latched When Control Bit = 1DATA ENTRY FORMATLatched WhenControl Bit = 1•Synthesizer lock is indicated by the extinguishingof the front panel LED indicator and a logic highon the fault FLAG 2 line (J1 pin 12C).•Always verify synthesizer lock after each new dataloading.Shift→RegisterOutControl BitSERVICE NOTESData→Lastbit A0LSB - - - A6MSB N0LSB - - - N9MSB R0LSB - - - R13MSBTROUBLESHOOTING CHARTSYMPTOM AREAS TO CHECK INDICATIONSI. Loop Fails To Lock 1. Check for:+8 Vdc at U16-3,+5 Vdc at U15-3+8 Vdc at Q8-C.Bad Regulation circuitry.Troubleshoot using standardprocedures.2. Check for 12.8 MHz reference at U6-2, and U6-3.Typical Levels:500 mVpp @ U6-22.5 Vpp @ U6-3Reference Osc. Module defective orsupply not present or low. Proceed toreference oscillator section II.3. Check for LO output @ J2.FLO ±5 MHz,0dBm nominal.LO tuning incorrect, or bufferamplifier bad. Proceed to LO tuningand power section III.4. Check Prescaler output @ U5-4.Typically: 2-4 MHz square wave @ 1.25 Vpp.If LO power is good, Check for 3.2Vdc @ U2-3. Replace U2, then U5 ifnecessary.5. Check for CLOCK, DATA, and ENABLE signals are reaching U6 pins 11,12, and 13 respec-tively. (0, 8V logic levels)Bad digital control circuitry.Troubleshoot using standardprocedures. Ensure all programmingsignals are present at J1.(CLOCK,DATA,ENABLE,A0,A1and A2)6. Check Ramp Signal @ U6-15. It should be 5 kHz nominal. If reference oscillator andprogramming signals are present forproper programming information.Last resort - replace Synthesizer ICU6.II. Reference OSC. not present or low power. 1. Check for 4.3 Vdc supply at junction of R5 and C41. Bad supply switch Q2 or wrongControl Signal Internal Osc.Troubleshoot using standardprocedures. Replace Y1 as last resort2. Check 12.8 MHz signal @ Q13-E. Should be approx. 350 mVpp.Bad buffer amplifier Q13.Troubleshoot using standardprocedures.LBI-38641F3
ASSEMBLY DIAGRAMRECEIVER SYNTHESIZER MODULE19D902781G1 & G2(19D902781, Sh1, Rev. 7)TROUBLESHOOTING CHART (Continued)SYMPTOM AREAS TO CHECK INDICATIONSIII. LO power low or tuned out of band. 1. Check tuning with 6 Vdc applied using test procedure. FLO±5 MHzLO tuning incorrect. Retunefollowing test procedure.2. Check DC bias at Buffer Amplifiers U1, U2, & U3 pin 3 Typ. 3.2 Vdc.Bad Buffer Amplifier. Replace badpart.IV. LO signal not present. (i.e. Q1 does not oscillate) 1. Check DC bias at Q1 drain. (Typ. +8Vdc) Replace Q1.2. Check DC bias at Q1 source. (Typ. +0.9 Vdc)LBI-38641F4
OUTLINE DIAGRAMRECEIVER SYNTHESIZER BOARD19D902664G1 & G2(19D902664, Sh. 1, Rev. 10)LBI-38641F5
SCHEMATIC DIAGRAMRECEIVER SYNTHESIZER BOARD19D902664G1(19D903621, Sh. 1, Rev. 4)LBI-38641F6
SCHEMATIC DIAGRAMRECEIVER SYNTHESIZER BOARD19D902664G1(19D903621, Sh. 2, Rev. 4)LBI-38641F7
SCHEMATIC DIAGRAMRECEIVER SYNTHESIZER BOARD19D902664G1(19D903621, Sh. 3, Rev. 4)LBI-38641F8
SCHEMATIC DIAGRAMRECEIVER SYNTHESIZER BOARD19D902664G2(19D903769, Sh. 1, Rev. 3)LBI-38641F9
SCHEMATIC DIAGRAMRECEIVER SYNTHESIZER BOARD19D902664G2(19D903769, Sh. 2, Rev. 3)LBI-38641F10
SCHEMATIC DIAGRAMRECEIVER SYNTHESIZER BOARD19D902664G2(19D903769, Sh. 3, Rev. 3)LBI-38641F11
PARTS LISTSYMBOL PART N0. DESCRIPTION— — — MISCELLANEOUS — — 2 19D902508P3 Chassis.3 19D902509P3 Cover.4 19D902555P1 Handle.5 19D902664G1 Receiver Synthesizer Board, (Used in G1).6 19A702381P506 Screw, thread forming: TORX, No. M3.5 - 0.6 X 6.7 19A702381P513 Screw, thread forming: TORX, No. M3.5 - 0.6 X 13.9 19B802690P1 RF Shielding Grommet.10 19D902824P1 RF Casting.11 19A702381P508 Screw, thd. form: No. 3.5-0.6 x 8.(Used in G1, G2, G1 and G2).17 19D902664G2 Receiver Synthesizer Board. (Used in G2).RECEIVER SYNTHESIZER BOARD19D902664G1 - G2— — — — CAPACITORS — — — C1 19A702236P28 Ceramic: 12 pF ±5%, 50 VDCW, temp coef 0±30 PPM. (Used in G2).C1 19A702236P23 Ceramic: 8.2 pF ±.25 pF, 50 VDCW, temp coef 0 ±30 PPM. (Used in G1).C2 19A702236P10 Ceramic: 2.2 pF ±2.5 pF, 50 VDCW, temp coef 0 ±30 PPM/°C. (Used in G2).C2 19A702236P8 Ceramic: 1.5 pF ±.25 pF, 50 VDCW. (Used in G1).C3 19A702236P38 Ceramic: 33 pF ±5%, 50 VDCW, temp coef 0 ±30 PPM/°C. (Used in G2).C3 19A702236P36 Ceramic: 27 pF ±5%, 50 VDCW, temp coef 0 ±30 PPM/°C. (Used in G1).C4 19A702236P9 Ceramic: 1.8 pF ±0.25 pF, 50 VDCW, temp coef 0 ±30 PPM.C5 19A702236P30 Ceramic: 15 pF ±5%, 50 VDCW, temp coef 0 ±30 PPM/°C. (Used in G2).C5 19A702236P28 Ceramic: 12 pF ±5%, 50 VDCW, temp coef 0 ±30 PPM. (Used in G1).C6 19A702236P36 Ceramic: 27 pF ±5%, 50 VDCW, temp coef 0 ±30 PPM/°C. (Used in G2).C6 19A702236P34 Ceramic: 22 pF ±5%, 50 VDCW, temp coef 0 ±30 PPM. (Used in G1).C7 19A702052P14 Ceramic: 0.01 µF ±10%, 50 VDCW.C8 19A702052P26 Ceramic: 0.1 µF ±10%, 50 VDCW.C9 19A702052P14 Ceramic: 0.01 µF ±10%, 50 VDCW.thruC12C13 19A702052P26 Ceramic: 0.1 µF ±10%, 50 VDCW.andC14C15 19A702052P5 Ceramic: 1000 pF ±10%, 50 VDCW.C16 19A702061P99 Ceramic: 1000 pF ±5%, 50 VDCW, thru temp coef. 0 ±30 PPM/ºC.C22C23 19A702052P5 Ceramic: 1000 pF ±10%, 50 VDCW.SYMBOL PART NO. DESCRIPTIONC24and 19A702236P32 Ceramic: 18 pF ±5%, 50 VDCW, tempC25 coef 0 ±30 PPMC26 19A702052P8 Ceramic: 3300 pF ±10%, 50 VDCW.C27 19A705205P2 Tantalum: 1 µF, 16 VDCW; thru sim to Sprague 293D.C30C31 19A702052P1 Ceramic: 220 pF ±10%, 50 VDCW.thruC33C34 19A702236P43 Ceramic: 51 pF ±5, 50 VDCW, ±30 PPM/°C.C35 19A703684P3 Metallized polyester: 2.2 µF ±10%, 50 VDCW.C36 19A703902P3 Metal: 0.047 µF ±10%, 50 VDCW.C37 19A702052P14 Ceramic: 0.01 µF ±10%, 50 VDCW.C38 19A702052P26 Ceramic: 0.1 µF ±10%, 50 VDCW.C39 19A702052P3 Ceramic: 470 pF ±10%, 50 VDCW.andC40C41 19A705205P6 Tantalum: 10 µF, 16 VDCW; sim to and Sprague 293D.C42C43 19A705205P2 Tantalum: 1 µF, 16 VDCW; sim to Sprague 293D.C44 19A702052P26 Ceramic: 0.1 µF ±10%, 50 VDCW.C45 19A702052P3 Ceramic: 470 pF ±10%, 50 VDCW.thruC47C48 19A705205P6 Tantalum: 10 µF, 16 VDCW; sim to and Sprague 293D.C49C50 19A702052P26 Ceramic: 0.1 µF ±10%, 50 VDCW.C51 19A701225P3 Electrolytic: 220 µF, -10+50%, 25 VDCW.C52 19A134227P5 Variable: 1.5 to 14 pF, 100 VDCW.C53 19A702052P26 Ceramic: 0.1 µF ±10%, 50 VDCW.C54 19A702052P14 Ceramic: 0.01 µF ±10%, 50 VDCW.C55 19A702052P26 Ceramic: 0.1 µF ±10%, 50 VDCW.andC56C57 19A702061P99 Ceramic: 1000 pF ±5%, 50 VDCW, and temp coef 0 ±30 PPM/°C.C58C59 19A702052P14 Ceramic: 0.01 µF ±10%, 50 VDCW.andC60C61 19A702061P99 Ceramic: 1000 pF ±5%, 50 VDCW, thru temp coef 0 ±30 PPM/°C.C69C70 19A702061P61 Ceramic: 100 pF ±5%, 50 VDCW, thru temp coef 0 ±30 PPM.C81C102 19A702236P25 Ceramic: 10 pF ±25pF, 50 VDCW, temp coef. 0 ±30 PPM/ºC.— — — — DIODES — — — — — CR1 19A703595P10 Diode, Optoelectric: Red; sim to HPHLMP-1301-010.D3 19A705377P1 Silicon, Hot Carrier: sim to MMB0201.D4 19A149674P1 Silicon, capacitive: sim to Toko KV1410.andD5RECEIVER SYNTHESIZER MODULE19D902781G1-G2ISSUE 4*COMPONENTS, ADDED, DELETED OR CHANGED BY PRODUCTION CHANGESSYMBOL PART NO. DESCRIPTIONR25 19B800607P151 Metal film: 150 ohms ±5%, 1/8 w. (Used in G1).R26 19B800607P181 Metal film: 180 ohms ±5%, 1/8 w. (Used in G2).R26 19B800607P151 Metal film: 150 ohms ±5%, 1/8 w. (Used in G1).R27 19B800607P181 Metal film: 180 ohms ±5%, 1/8 w.andR28R29 19B800607P103 Metal film: 10K ohms ±5%, 1/8 w.R30 19B800607P270 Metal film: 27 ohms ±5%, 1/8 w. (Used in G2).R30 19B800607P390 Metal film: 39 ohms ±5%, 1/8 w. (Used in G1).R31 19B800607P270 Metal film: 27 ohms ±5%, 1/8 w.R32 19B800607P472 Metal film: 4.7K ohms ±5%, 1/8 w.andR33R34 19B800607P103 Metal film: 10K ohms ±5%, 1/8 w.andR35R36 19B800607P104 Metal film: 100K ohms ±5%, 1/8 w.andR37R38 19B800607P682 Metal film: 6.8K ohms ±5%, 1/8 w.R42 19B800607P104 Metal film: 100K ohms ±5%, 1/8 w. (Used in G2).R42 19B800607P333 Metal film: 33K ohms ±5%, 1/8 w. (Used in G1).R43 19B800607P333 Metal film: 33K ohms ±5%, 1/8 w.R44 19B800607P105 Metal film: 1M ohms ±5%, 1/8 w.R45 19B800607P472 Metal film: 4.7K ohms ±5%, 1/8 w.R46 19B800607P201 Metal film: 200 ohms ±5%, 1/8 w. (Used in G2).R46 19B800607P181 Metal film: 180 ohms ±5%, 1/8 w. (Used in G1).R47 19B800607P271 Metal film: 270 ohms ±5%, 1/8 w.R48 19B800607P181 Metal film: 180 ohms ±5%, 1/8 w.R49 19B800607P103 Metal film: 10K ohms ±5%, 1/8 w.thruR51R52 19B800607P473 Metal film: 47K ohms ±5%, 1/8 w.thruR54R55 19B800607P222 Metal film: 2.2K ohms ±5%, 1/8 w.R56 19B800607P510 Metal film: 51 ohms ±5%, 1/8 w.R57 19B800607P473 Metal film: 47K ohms ±5%, 1/8 w.R58 19B800607P681 Metal film: 680 ohms ±5%, 1/8 w.R59 19B800607P222 Metal film: 2.2K ohms ±5%, 1/8 w.R60 19B800607P102 Metal film: 1K ohms ±5%, 1/8 w.thruR63R64 19B800607P510 Metal film: 51 ohms ±5%, 1/8 w.R65 19B800607P103 Metal film: 10K ohms ±5%, 1/8 w.andR66R67 19B800607P473 Metal film: 47K ohms ±5%, 1/8 w.andR68SYMBOL PART NO. DESCRIPTIONJ1 19B801587P7 Connector, DIN: 96 male contacts, rightangle mounting; sim to AMP 650887-1.J2 19A115938P24 Connector, receptacle.thruJ4— — — — INDUCTORS — — — L2 19A700024P13 Coil, RF: 1.0 µH ±10%.thruL4L5 19A700024P15 Coil, RF: 1.5 µH ±10%.L6 19A705470P13 Coil: 0.10 µH ±20%. (Used in G2).L6 19A705470P12 Coil, fixed. (Used in G1).L7 19A705470P24 Coil, fixed: 1.5 µH ±10%.L8 19A705470P10 Coil, fixed: 56 nH ±20%. (Used in G2).L8 19A705470P9 Coil, Fixed: 47 nH; sim to Toko 380NB-47nM. (Used in G1).L9 19A705470P10 Coil, fixed: 56 nH ±20%. (Used in G2).L9 19A705470P9 Coil, Fixed: 47 nH; sim to Toko 380NB-47nM. (Used in G1).L10 19C851001P3 Coil, RF: sim to Paul Smith SK-901-1. (Used in G2).L10 19C851001P1 Coil, RF: sim to Paul Smith SK901-1. (Used in G1).L18 19A705470P13 Coil: 0.10 µH ±20%— — — TRANSISTORS — — — Q1 19A702524P2 N-Type, field effect; sim to MMBFU310.Q2 19A700076P2 Silicon, NPN: sim to MMBT3904, low thru profile.Q7Q8 19A700059P2 Silicon, PNP: sim to MMBT3906, low profile.Q9 19A700076P2 Silicon, NPN: sim to MMBT3904, low thru profile.Q13— — — — RESISTORS— — — — R1 19B800607P680 Metal film: 68 ohms ±5%, 1/8 w.R2 19B800607P100 Metal film: 10 ohms ±5%, 1/8 w.thruR9*R10 19B800607P1 Metal film: 0 ohms.R11 19B800607P183 Metal film: 18K ohms ±5%, 1/8 w.R12 19B800607P330 Metal film: 33 ohms ±5%, 1/8 w.R13 19B800607P270 Metal film: 27 ohms ±5%, 1/8 w.R14 19B800607P470 Metal film: 47 ohms ±5%, 1/8 w.andR15R16 19B800607P330 Metal film: 33 ohms ±5%, 1/8 w.R17 19B800607P270 Metal film: 27 ohms ±5%, 1/8 w.R18 19B800607P180 Metal film: 18 ohms ±5%, 1/8 w.R19 19B800607P100 Metal film: 10 ohms ±5%, 1/8 w.R20 19B800607P103 Metal film: 10K ohms ±5%, 1/8 w.R21 19B800607P472 Metal film: 4.7K ohms ±5%, 1/8 w.R22 19B800607P271 Metal film: 270 ohms ±5%, 1/8 w.R23 19B800607P103 Metal film: 10K ohms ±5%, 1/8 w.R24 19B800607P201 Metal film: 200 ohms ±5%, 1/8 w.LBI-38641F12
IC DATAPARTS LIST & PRODUCTION CHANGESSYMBOL PART NO. DESCRIPTIONR70 19B800607P102 Metal film: 1K ohms ±5%, 1/8 w.thruR72R73 19B800607P103 Metal film: 10K ohms ±5%, 1/8 w.thruR76R77 19B800607P101 Metal film: 100 ohms ±5%, 1/8 w.andR78R79 19B800607P102 Metal film: 1K ohms ±5%, 1/8 w.thruR88— — INTEGRATED CIRCUITS — U1 19A705927P1 Silicon, bipolar: sim to Avantek thru MSA-0611.U4U5 19A149944P201 Dual Modulus Prescaler: sim to MC12022A.U6 19B800902P5 Synthesizer, custom: CMOS, serial input.U8 19A702293P3 Linear: Dual Op Amp; sim to LM358D.andU9U10 19A703471P320 Digital: 3-Line To 8-Line Decoder; sim to 74HC138.U12 19A703483P302 Digital: Quad 2-Input NAND Gate; and sim to 74HC00.U13U14 19A702705P4 Digital: Quad Analog Switch/Multiplexer; sim to 4066BM.U15 19A704971P8 Voltage Regulator, Positive: sim to Motorola MC78M05CDT.U16 19A704971P10 Voltage Regulator, Positive: sim to Motorola MC78M08CDT.— — — — CRYSTALS — — — Y1 19B801351P12 Crystal Oscillator; 14.850 MHz, temperature compensated.U1 thru U419A705927P1Silicon Bipolar ICU519A149944P201Modulus Prescaler120324567810 1112131415161718199U619B800902P7SynthesizerPRODUCTION CHANGESChanges in the equipment to improve or to simplify circuits are identified by a"Revision Letter", which is stamped after the model number of the unit. The revisionstamped on the unit includes all previous revisions. Refer to the Parts List fordescriptions of parts affected by these revisions.REV. A - RECEIVER SYNTHESIZER BOARD 19D902664G1 & G2To improve regulator operation at low supply voltage. Changed resistorR10. Resistor R10 was 10 ohms (19B800607P100).REV. B - RECEIVER SYNTHESIZER BOARD 19D902664G1 & G2To accommodate SOG synthesizer IC package U6 (PLCC packagediscontinued) and make provision for RC compensation network (R89,C82) in 10-Volt regulator circuit. Resistor R89 and capacitor C82 are notinstalled. Modified printed wire board layout (Printed wire board changedfrom 19D902665P1R1 to 19D902665P1R2). Changed U6. SynthesizerU6 was 19B800902P5.REV. A - RECEIVER SYNTHESIZER MODULE 19D902781G1 & G2To install RF shielding grommets. Installed item 9 RF shielding grommets(19B705470P1) on three BNC connectors of input/output RF ports.REV. C - RECEIVER SYNTHESIZER BOARD 19D902664G1 & G2To add filtering in the output circuit of the pre-scaler buffer amplifier.Changed capacitor C16. Capacitor C16 was 19A702052P3 (470 pF).Added capacitor C102 and inductor L18. Changed resistor R24. ResistorR24 was 19B800607P510 (51 Ohms).LBI-38641F13
IC DATAU8 & U919A702293P2Dual Operational AmplifierU1019A703471P120Decoder/DemuxU12 & U1319A703483P302Logic Gate/InverterU1419A702705P4Quad Analog SwitchU1619A70497P10+8V RegulatorU1519A704971P8+5 RegulatorY119B801351P12Crystal OscillatorLBI-38641F14
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