EMCEE Broadcast TU1000F UHF LPTV Translator User Manual TTU1000F Mnl Cover Pg 1

EMCEE Broadcast Products UHF LPTV Translator TTU1000F Mnl Cover Pg 1

TU1000F Manual

Broadcast ProductsP.O. Box 68, White Haven, PA 18661 Phone: (570) 443-9575 FAX: (570) 443-9257MDS MMDS ITFS LPTVNorth America South America Europe Asia Australia AfricaSince 1960TU1000F V/USOLID STATE1000W UHF TRANSLATOR
TU1000F V/USOLID STATE1000W UHF TRANSLATOR02/00
TABLE OF CONTENTSI. THE TU1000F V/U TRANSLATOR1.1 Introduction1.2 Specifications1.3 Installation1.4 Operation1.5 Warranty and Parts OrderingII. CIRCUIT DESCRIPTION2.1 Receiver Drawer2.2 Exciter/Upconverter Drawer2.3 Power Splitter2.4 Dual 300W Power Amplifier Drawer2.5 Power Combiner2.6 Metering Coupler2.7 Front Panel2.8 Output FilterIII. MAINTENANCE3.1 Periodic Maintenance Schedule3.2 Recommended Test Equipment3.3 Troubleshooting3.4 Translator Alignment3.5 Output Power Calibration3.6 Precorrection Adjustment3.7 Control Board Setup3.8 Remote Monitor Signal Levels3.9 Spare Modules and Components ListsIV. DATA PAKV. SCHEMATIC DIAGRAMS
iSECTION ITHE TU1000F V/U TRANSLATOR1.1 Introduction ............................................................ 1 11.2 Specifications .......................................................... 1 11.3 Installation ............................................................. 1 21.4 Operation .............................................................. 1 31.5 Warranty and Parts Ordering ............................................ 1 4
1 1SECTION ITHE TU1000F V/U TRANSLATOR1.1 Introduction:The EMCEE TU1000F V/U Translator is rated to provide 1000 watts peak visual and 50 wattsaverage aural power on any FCC specified channel extending from 470 to 806MHz. The TU1000Fis completely solid-state providing maximum performance and reliability. It is comprised of aReceiver Drawer, a 20 Watt UHF Exciter/Upconverter, two Dual 300W Power Amplifier assembliesand a panel for power distribution and metering. The TU1000F is easy to service and maintain whileRF alignment is practically nonexistent. A number of front panel indicators are included whichdisplay the results of the translator's diagnostic/control circuitry.The TU1000F Translator is designed for the express purpose of broadcasting as authorized by theU.S. Federal Communications Commission under Part 74, Subpart G, of the FCC Rules andRegulations.1.2 Specifications:Output Power 1000W peak visual50W average auralEmissions 5M75C3F visual250KF3E auralColor Transmission NTSC, PAL, or SECAMOutput Frequency Range 470-806MHzInput Frequency Range 54-88MHz (FCC Ch. 2-60)174-216MHz (FCC Ch. 7-13)470-806MHz (FCC Ch. 14-69)Frequency Stability ±1kHzVisual Output Power Stability ±0.5dBSpurious Products 60dB below peak syncHarmonics 60dB below peak syncIn-band Intermodulation (IM3)52dB below peak syncDifferential Gain 5%Differential Phase ±3Frequency Response ±1.0dB
1 2Envelope Delay ±50nsecOutput Impedance 50 ohms (7/8" EIA flange connector)RF Input Level 70dBm to 30dBmRF Input Impedance 50 ohms unbalanced (N connector)Video Signal to Noise 50dB @ 47dBm inAudio Distortion <1%Aural FM Noise < 55dBAmbient Temperature 30 C to +50 CPower Requirements 230Vac ± 15% @ 50/60Hz, 3.8kWMechanical Dimensions 69"H x 23"W x 29"DWeight 350 lb.1.3 Installation:Except where otherwise noted, the connectors mentioned in the following instructions are locatedon the rear of the translator. 1. After unpacking the translator, a thorough inspection should be conducted to reveal anydamage which may have occurred during shipment. If damage is found, immediately notifythe shipping agency and advise EMCEE Broadcast Products Customer Service or its fieldrepresentative. Also check to see that any connectors, cables or miscellaneous equipment,which may have been ordered separately, are included. 2. Place the translator in a clean, weatherproof environment providing adequate ventilation forthe exhaust fans at the top of the cabinet. It is important to maintain the translator's ambienttemperature within the 30 C and +50 C limits. Cooler ambient temperatures will provideincreased reliability. 3. Place the translator in its permanent location near a single-phase receptacle that supplies230Vac at 50/60Hz. The ac source should have a minimum power capacity of 5kW.IMPORTANTDo not apply ac power to the translator at this time since its RF output must be properlyterminated before being placed in operation.
1 3 4. Set all circuit breakers and switches, including the customer's incoming ac line breaker, tothe OFF position. Place an appropriate ac power line protector (surge suppressor) across theac line that supplies the translator. 5. With the appropriate cables (customer supplied), connect the receiving antenna to the RF IN“N” connector located on the top rear panel of the translator cabinet. 6. Connect the transmitting antenna cable to the 7/8" EIA flange connector marked RF OUTPUTlocated at the top, rear, right-hand corner of the cabinet (as seen from the front). 7. Verify that the power cords of the Receiver and Exciter drawers are plugged into thereceptacle at the bottom of the cabinet inside the rear door. Check all other factory installedRF cables and DC wire harnesses for tight connections. 8. Using the 4-prong, twist lock, female plug supplied with the translator, fabricate an ac powercord and plug it into the translator's AC MAINS connector at the top left rear (as seen facingthe front of the cabinet) of the translator's cabinet. Connect the other end of the power cordinto an appropriate electrical outlet.1.4 Operation:Assuming the installation instructions of Section 1.3 have been completed and the translator isreceiving a signal of appropriate frequency and amplitude, proceed with the following steps to placethe translator in operation. Except where otherwise noted, the controls, switches, and indicatorsmentioned in these steps are located on the front of the translator. 1. Close the transmission site’s ac mains breaker. Place the Receiver front panel OPERATE/ALIGN switch to OPERATE and its AC POWER circuit breaker to ON. Verify that theCARRIER PRESENT indicator is illuminated green. 2. Turn the Exciter/Upconverter POWER ADJUST control fully counterclockwise and place itsOPERATE/STANDBY switch to STANDBY, its OPERATE/ALIGN switch to OPERATE.Place the Control/Metering Panel’s AC POWER circuit breaker and the Exciter POWER ONbreaker both to the on/up position. Then verify the following responses of the translator:a. The fans of the translator should be operating. The Exciter exhausts air out the rear ofthe drawer while the Power Amplifier drawer exhausts air through the cabinet top withthe aid of cabinet-mounted exhaust fans.b. The Exciter's OPERATE, SYNTH LOCK, and DRIVER AMP indicators should beilluminated green.c. The Exciter’s TEMP EXCITER, ON, FINAL BIAS and VSWR OVLD indicators shouldbe extinguished.d. The TEMPERATURE, VSWR OVLD and COLLECTOR BIAS indicators of each PowerAmplifier should be extinguished.e. The Control/Metering Panel’s four Amplifier Status indicators should be illuminatedgreen.
1 4 3. Place the Exciter’s OPERATE/STANDBY switch to OPERATE. Then verify the followingresponses of the translator:a. The Exciter's OPERATE, SYNTH LOCK and DRIVER AMP indicators should remainilluminated green.b. The Exciter's ON and FINAL BIAS indicators should be illuminated green while theVSWR OVLD and TEMP indicators remain extinguished.c. The TEMPERATURE indicator of each Power Amplifier drawer should remainextinguished while the COLLECTOR BIAS indicators are illuminated green.d. The Control/Metering Panel’s AMPL 1 through AMPL 4 indicators should remainilluminated green. 4. Place the Control/Metering Panel's meter switch to FWD and turn the Exciter's POWERADJUST control clockwise until a 100% indication appears on the Control/Metering Panel'sRF POWER meter. Set the Exciter’s % meter to display FWD power. Note that the metermay show a reading less than 100%. This is appropriate. 5. Place the Control/Metering Panel's meter switch to REFLD and verify that the meter indicatesno more than 10% returned power. If the reflected power is more than 10%, shut down thetranslator and check the VSWR of the transmitting antenna and its associated cable. 6. Place the Control/Metering Panel's meter switch to FWD for constant monitoring of thetranslator's final output power.The translator is now in operation. Check its coverage area for clean, sharp television reception.If the reception or picture quality is unsatisfactory, examine the amount of power delivered to thetransmitting antenna (see Section 3.5) and, if necessary, examine the antenna orientation, antennaVSWR, and transmission line VSWR to insure maximum radiation in the proper direction.1.5 Warranty and Parts Ordering:Warranty – EMCEE warrants its equipment to be free from defects in material and workmanship fora period of one year after delivery to the customer. Equipment or components returned as defective(prepaid) will be, at our option, repaired or replaced at no charge as long as the equipment orcomponent part in question has not been improperly used or damaged by external causes(e.g., water, ac line transients or lightning). Semiconductors are excepted from this warranty andshall be warranted for a period of not more than ninety (90) days from date of shipment. Equipmentor component parts sold or used by EMCEE, but manufactured by others, shall carry the samewarranty as extended to EMCEE by the original manufacturer.Equipment Returns – If the customer desires to return a unit, drawer, or module to EMCEE forrepair, follow the procedure described below: 1. Contact EMCEE Customer Service Department by phone or fax for a Return AuthorizationNumber.
1 5 2. Provide Customer Service with the following information:Equipment model and serial numbers.Date of purchase.Unit input and output frequencies.Part number (PN) and Schematic Diagram designator if a module is being sent.Detailed information concerning the nature of the malfunction.The customer shall designate the mode of shipping desired (e.g., Air Freight, UPS, Fed Ex, etc.).EMCEE will not be responsible for damage to the material while in transit. Therefore, it is of utmostimportance that the customer insure the returned item is properly packed.Parts Ordering – If the customer desires to purchase parts or modules, utilize the followingprocedure: 1. Contact EMCEE Customer Service by phone or fax indicating the customer's purchase ordernumber. If the purchase order number is provided by phone, written confirmation of the orderis required. 2. Also provide:The equipment model and serial number.The unit input and output frequencies.The quantity, description, vendor, number, and designation of the parts needed as found inthe Parts Lists subsection of this manual.If a module is required, give the part number (PN) and Schematic Diagram designator(e.g., 10331209).Designate the mode of shipping desired (e.g., Air Freight, UPS, Fed Ex, etc.).Shipping and billing addresses.Spare and Replacement Parts – The Spare Modules and Components section of this manualprovides a detailed listing of the modules and some discrete components contained within thetranslator. The listing contains those modules or components considered to be essential bench-stock items and should be available to the technician at all times. The Schematic or InterconnectionDiagram is the governing document of this manual. Should there be a discrepancy between amodules or components list and a diagram, the diagram takes precedence. Such a discrepancy ispossible since manufacturing changes cannot always be incorporated immediately into theinstruction manual.Component Referencing – The translator consists of a number of modules and components mountedin four drawers, a number of components mounted on panels, and several cabinet-mountedcomponents and modules. Components mounted in a module which is included in a drawer takethe drawer number and the module number in addition to a component number. Thus the referencedesignator A2A1Q1 means transistor Q1 in module A1 of drawer A2. Components mounted in adrawer take only the drawer number and a component number (e.g., A2M1 designates meter M1 ofdrawer A2). Components mounted directly to a panel take only the panel number and a componentnumber. Components and modules mounted directly to the cabinet take only a component ormodule number.
1 6For EMERGENCY technical assistance, EMCEE offers a toll free, 24-hour, 7-day-a-weekcustomer service hot line: 1-800-233-6193.
iiaSECTION IICIRCUIT DESCRIPTION2.1 Receiver Drawer ....................................................... 2 12.1a VHF/UHF Remote Preamplifier (Optional) ................................ 2 22.1b VHF Bandpass Filter ................................................ 2 22.1c UHF Bandpass Filter ................................................ 2 22.1d Crystal Oscillator ................................................... 2 32.1e X2 Multiplier and X4 Multiplier ......................................... 2 32.1f X16 Multiplier ...................................................... 2 42.1g 10MHz Reference Oscillator ........................................... 2 52.1h VHF Synthesizer Low Band ........................................... 2 52.1i VHF Synthesizer High Band........................................... 2 62.1j UHF Synthesizer ................................................... 2 72.1k Downconverter/Preamplifier ........................................... 2 82.1l IF SAW Filter/Amplifier .............................................. 2 82.1m IF AGC Amplifier ................................................... 2 92.1n Automatic-On..................................................... 2 102.1o Limiter/Output AGC Control .......................................... 2 102.1p Aural Notch Filter .................................................. 2 112.1q Multioutput Power Supply ............................................ 2 112.1r Digital Code ID Unit (Optional) ........................................ 2 122.2 Exciter/Upconverter Drawer ............................................ 2 132.2a Linearizer ........................................................ 2 142.2b IF/Upconverter .................................................... 2 142.2c UHF Synthesizer .................................................. 2 162.2d Reference Oscillator ................................................ 2 172.2e UHF Bandpass Filter ............................................... 2 172.2f 2 Watt UHF Amplifier ............................................... 2 172.2g 20 Watt UHF Amplifier .............................................. 2 182.2h Metering Coupler .................................................. 2 192.2i Metering Detector.................................................. 2 192.2j Control Board ..................................................... 2 202.2k Power Supplies ................................................... 2 222.3 Power Splitter ......................................................... 2 222.4 Dual 300W Power Amplifier Drawer ..................................... 2 222.4a 300W UHF Amplifier ............................................... 2 232.4b Status Display .................................................... 2 232.4c +28V Power Supply ................................................ 2 242.5 Power Combiner ...................................................... 2 242.6 Metering Coupler ...................................................... 2 242.7 Front Panel ........................................................... 2 242.7a Metering Detector.................................................. 2 252.7b Control Board ..................................................... 2 252.8 Output Filter .......................................................... 2 28
2 1SECTION IICIRCUIT DESCRIPTION2.1 Receiver Drawer:Interconnection Diagram 30383094/Rev 54 A1 (Vectron Oscillator with Multiplier)Interconnection Diagram 30383104/Rev 55 A1 (Synthesizer)RF IN 70dBm to 30dBm peak visualIF OUT 6dBmLO SAMPLE 0dBmThe Receiver drawer provides highly selective VHF or UHF to IF signal conversion, IFamplification, and prevention of unauthorized radiation if the proper input signal is not received.Signal conversion is accomplished via a VHF or UHF Bandpass Filter (FL1), and a Downconverter/Preamplifier (A1). The LO for downconversion is provided by one of six sources depending uponthe application. A high stability crystal oscillator (G1) with a X2, X4 or X16 Multiplier (A4) is usedwhen a frequency offset is required when receiving VHF Low Band (Ch.2-6), VHF High Band(Ch.7-13) or UHF (Ch.14-69) respectively. If no frequency offset is required, the correspondingSynthesizer (A4) and 10MHz Reference Oscillator (A5) are used. IF amplification and filtering arefurnished through the IF Amplifier w/SAW Filter (A2) and the IF AGC Amplifier (A3). The AuralNotch Filter (FL2) allows for attenuation of the aural carrier to facilitate a reduction of in-band thirdorder intermodulation products or to maintain the minimum visual to aural carrier ratio. Finally, a6dB attenuator reduces the IF signal to a level that is within the input range of the Exciter/Upconverter (A2).The Receiver drawer also insures that the translator does not exceed or deviate from its ratedoutput power while receiving signal variations of up to 40dB ( 70dBm to 30dBm). This functionis accomplished through a complex gain control system employing the IF AGC Amplifier's variablepin diode attenuator and a Limiter/Output AGC (PC1). The IF AGC Amplifier's variable pin diodeattenuator is controlled by the input AGC circuit of the IF AGC Amplifier and the output AGC circuitof the Limiter/Output AGC. As the received signal increases, the input AGC circuit of the IF AGCAmplifier provides an increase in the AGC voltage applied to the variable pin diode attenuator.This condition causes an increase in the attenuation provided by the variable pin diode attenuator.As a result, the IF output of the Receiver drawer is held constant at approximately 6dBm (±1dB)throughout the 40dB variation in the received signal.The input AGC circuit alone does not provide for controlling changes in amplifier gain occurringafter the IF section of the Receiver. (An amplifier's gain may change during warm-up, over longperiods of time, and under varying temperatures.) The output gain control circuit of the Limiter/Output AGC is incorporated to monitor and correct any changes in the translator's output power.The output AGC circuit controls the gain of the IF AGC Amplifier by monitoring the dc voltage thatdrives the translator's % Power meter. Any deviation from the translator's correct output power willshift the metering voltage, causing the output AGC circuit to vary the biasing on the IF AGCAmplifier's variable pin diode attenuator. The attenuation will vary in such a way that any powerfluctuations at the output of the translator will be counteracted.Should the Receiver drawer experience a temporary loss of signal (fading, etc.), the limiter circuitof the Limiter/Output AGC serves to prevent overdriving the translator's power amplifier modules.(A decrease in the received signal reduces the AGC voltage and consequently increases the gain
2 2of the IF AGC Amplifier.) When the received signal regains its strength, the limiter circuit willmomentarily attenuate ( 20dB) the IF output of the Receiver drawer until adequate AGC voltageis developed to control the Receiver's overall gain.In the event of a significant reduction or loss of the Receiver's input signal for more than30 seconds, an Automatic-On circuit (PC2) will prevent the radiation of noise by shutting down theReceiver. Should the VHF or UHF input signal to the Receiver fall below the minimum acceptablelevel of 70dBm, the accompanying AGC voltage will fall below a preset Auto-On Thresholdvoltage. This in turn causes Auto-On relay K1 to de-energize which opens the interlock loop andshuts down the translator.2.1a VHF/UHF Remote Preamplifier: (OPTIONAL)Scala Model 8000Specifications See Data Pak2.1b VHF Bandpass Filter:Schematic A280-92/Rev 1 (Ch.2-6) A1FL1Schematic A280-89/Rev 1 (Ch.7-13) A1FL1Frequency Response (J1-J2) 7MHz @ 1dBInsertion Loss (J1-J2) 2dB Max.The high band VHF bandpass filter is a two-section overcoupled circuit that rejects all frequenciesother than the single VHF channel to which it is tuned. The bandpass filter is adjusted to providea 7MHz @ 1dB frequency response with an insertion loss of approximately 2dB or less. In thefilter, inductors L3 and L4, in conjunction with stagger-tuned capacitors C1 through C4, provide therequired bandpass response. Capacitor C5 also effects the response by changing the effectivecoupling between the two circuits. Impedance matching is accomplished by inductors L1 and L2along with variable capacitors C1 and C2.2.1c UHF Bandpass Filter:Schematic 10331209/Rev 52 (Ch.14-83) A1FL1Frequency Response 7MHz @ 1dBInsertion Loss 3dB Max.The filter is composed of three overcoupled, 1/4 wave coaxial cavities that reject all frequenciesother than the single UHF channel to which it is tuned. The UHF Filter provides a 7MHz bandwidthat 1dB and has an insertion loss of 3dB or less. In the filter, components L2, L3 and L4 are solidbrass rods acting as 1/4 wave shorted transmission lines. The length of these lines, controlled byvariable capacitors C1, C2 and C3, dictates the resonant frequency of the filter. Inductors L1 andL5 link couple the UHF signal into and out of the filter. The position of these two inductors inrelation to the 1/4 wave brass rods determines the filter's input and output impedance, as well as
2 3skirt selectivity and insertion loss. The Variable Coupling Barriers regulate the amount of signalpassed between the coaxial cavities and therefore control the bandwidth of the filter.2.1d Crystal Oscillator:Vectron CO-254D57 A1G1Supply Voltage 28VOutput Power +7dBmOperating Temperature 30 C to +70 CStability ±5 x 10-7The CO-254D57 is a high stability, temperature-compensated crystal oscillator (TCXO)manufactured by Vectron Laboratories, Inc. This oscillator, in conjunction with a X2, X4 or X16Multiplier, is used in place of the EMCEE Synthesizer when ±10kHz precision offset is required.See the Data Pak for further information.2.1e X2 Multiplier and X4 Multiplier:Schematic B280-35/Rev E (Ch.2-6) A1A4 (X2 Multiplier)Schematic C331-24/Rev D (Ch.7-13) A1A4 (X4 Multiplier)Multiplier Q1 Q2 Q3Collector V 25 15 15Output Power 10-40mWOutput Frequency Osc. 2nd/4th HarmonicThe VHF Multiplier consists of an amplifier and two doubler stages fed by the fundamentalfrequency of the crystal oscillator. Transistor Q1 is an untuned class A VHF amplifier coupled toa resonated idler loop tuned to the fundamental frequency (series circuit L3 and C7). TransistorQ2 is a class AB X2 frequency multiplier that feeds an LC series circuit (L5, C12) tuned to thesecond harmonic. Capacitors C13 through C17 and inductors L6 through L8 make up athree-section bandpass filter which passes only the second harmonic frequency. If the multiplieris a X4 type, transistor Q3 is a class C frequency doubler with both input and output tuning. Tuningconsists of a second harmonic idler circuit (L9 and C19) at the input and an output network (L12,C22 and C23) that is tuned to the oscillator's 4th harmonic. C26 through C29 and inductors L13and L14 make up a two-section bandpass filter tuned to pass the oscillator's fourth harmonic. AnLO sample ( 1mW) port (J3) is provided on the front panel of the translator drawer for convenientmonitoring or mixing.
2 42.1f X16 Multiplier:Schematic Diagram 30367226/Rev A A1A4INPUT power 0 to +10dBmTypical +7dBmLO OUT (J2)Output power +15dBm Min.Output frequency 16th harmonic of inputThe X16 Multiplier provides three sections of frequency multiplication to generate the LO necessaryfor downconverting UHF channels to IF.Section 1 consists of a frequency multiplier (A1), a bandpass filter (FL1), and an amplifier (U1).A1 produces harmonics from the input signal of the crystal oscillator. The desired harmonic fromA1 is the fourth, whose level should typically be 30dB below the oscillator level. FL1 is a narrowbandpass filter, which also employs two tunable notch filters. When properly tuned, FL1 has atypical insertion loss of 2 to 2.5dB. The notch filters are tuned to the 3rd and 5th harmonicsproviding an additional minimum attenuation of 15dB to these harmonics. Output level from FL1is approximately 28 to 32dBm. U1 is a monolithic amplifier with a typical gain of 33dB at thesefrequencies. U1 provides the nominal level of 0dBm for the next section of frequencymultiplication.Section 2 consists of a frequency multiplier (A2), a filter FL2, and a two-stage amplifier (U2, U3).A2 produces harmonics of the signal taken from the previous section. The desired frequency fromthis section is the 2nd harmonic of the input (8th harmonic of OSC.). The output level of A2 at the2nd harmonic is typically 15dBm. FL2 is a tunable microstrip bandpass filter. The filter has afrequency range of 250-470MHz, an insertion loss of 2dB and is tuned to pass the 2nd harmonicof A2. The output level from FL2 is a nominal 17dBm. U2 and U3 are monolithic amplifiers witha combined typical gain of 25dB. These are used to produce an input level of +8dBm to the thirdsection.Section 3 consists of a frequency multiplier (A3), two different stages of amplification (U4 and U5,U6), and two filters (FL3, FL4). A3 is used to produce harmonics of the frequency from Section 2.The desired frequency from A3 is the second harmonic of its input (16th of OSC.). Output levelof the second harmonic from A3 is typically 6dBm. U4 is used to amplify the output of A3 beforefiltering by FL3. The output level of U4 at the 2nd harmonic of A3 is at a nominal 2dBm level. FL3is a tunable microstrip bandpass filter with a frequency range of 500-940MHz and an insertion lossof 2dB. The filter is tuned to the 2nd harmonic of A3. The output level of FL3 is 0dBm. U5 is amonolithic amplifier with a 12dB gain. U5 is run into compression allowing the oscillator level tovary while the output of U5 remains constant. The output of U5 drives U6, another monolithicamplifier with a gain of 11.5dB. This amplifier is also operated in compression for the same reasonas U5. The output of U6 is +18 to +20dBm. FL4 is tuned for the second harmonic from A3 andprovides additional filtering to suppress the undesired harmonics from previous frequencymultiplication. Secondly, the filter removes any additional undesired signals caused bycompressing amplifiers U5 and U6. The output level from FL4 is typically +16dBm to +18dBm.
2 52.1g 10MHz Reference Oscillator:Schematic Diagram 10368037/Rev B A1A4A210MHz REF. OUT (J1, J2) 3.5V P/P square waveThe Reference Oscillator provides a 10MHz reference signal for the Synthesizer (A4A1). Thismodule is centered around a 10MHz temperature-compensated crystal oscillator (G1). The outputfrom G1 is applied to two exclusive-OR gates used as inverting buffers. The output signal fromeach gate is a 10MHz low-level square wave with a frequency stability of 0.3 parts per million(PPM).2.1h VHF Synthesizer Low Band:Schematic Diagram 30362427/Rev C A1A4A110MHz REF. IN (J1) 3.5V P/P square waveLO OUT (J2) +15.25dBm min.SYNTH. LOCK (Pin A of J4) logic high (locked)logic low (unlocked)The VHF Synthesizer is a phase-lock loop type and uses one of the 10MHz reference signals fromthe Reference Oscillator (A4A2) and develops a programmable LO signal for the Mixer (MX1) inthe Downconverter/Preamplifier (A1). The frequency of the LO signal is calculated as the sum ofthe visual IF carrier and the visual VHF carrier of the specified input channel. The LO signal'sfrequency is programmed by the setting of switches S1 through S4 which are accessible throughthe module's cover. The relationship between the setting of these switches and the resulting LOfrequency is provided in Table 2 3 for each VHF channel.A 10MHz reference signal is brought in from the Reference Oscillator (A4A2) through J1, 10MHzIN. Both sections of U4 perform binary divide-by-5 counting to provide a 400kHz signal to theOSCin input of U1, pin 27. To create U1's internal 50kHz reference signal, U1 performs a binarydivide-by-8 operation on the OSCin signal.Controlling the VCO, G1, is the output of op-amp U3. U3 compares and integrates the 0/V and 0/Rphase detector outputs of U1. The output of U3 is filtered to create the dc control voltage for theVCO. The output of G1, RF OUT, is amplified by U5 and available as the Receiver's LO at J2,OUT.The output of G1 is also amplified by U6 and then fed to a ÷32/÷33 prescaler, U2. After prescaling,the signal is connected to U1 pin 1, Fin, from U2 pin 4, OUT, completing the loop. The prescalingfactor of U2 is selected by the MOD CONTROL, pin 9, of U1. Switches S1 to S4 set twodivide-by-ratios, counters A and N, within U1. When divide-by-A is being performed on the signalat Fin, MOD CONTROL is set high, selecting ÷32 in the prescaler, U2. MOD CONTROL goes lowfor divide-by-N selecting ÷33 in U2.The A and N counters form a binary number from A0 to N9 with A0 being the LSB and N9 beingthe MSB. The decimal equivalent of this number, when multiplied by the internal referencefrequency 50kHz, gives the synthesizer's output frequency. Hence, for NTSC operation, A0 andA1, pins 21 and 23 on U1, are grounded. For PAL operation, A0 and A1 are made high by cutting
2 6the traces from pins 21 and 23 to ground thereby adding the 150kHz to the LO that is characteristicof the PAL system.When the synthesizer is locked onto a frequency, LD is high. This saturates Q1 and puts a low onSYNTH LOCK. C28 provides a time delay to ensure that the synthesizer has successfully lockedbefore indicating so on the SYNTH LOCK line. For an unlocked condition, LD pulses lowpreventing C28 from charging and saturating Q1. +5V is therefore present on the SYNTH LOCKline for the unlocked condition.2.1i VHF Synthesizer High Band:Schematic Diagram 30362003/Rev D A1A4A110MHz REF. IN (J1) 3.5V P/P square waveLO OUT (J2) +15.25dBm min.SYNTH. LOCK (Pin A of J4) logic high (locked)logic low (unlocked)The VHF Synthesizer is a phase-lock loop type and uses one of the 10MHz reference signals fromthe Reference Oscillator (A4A2) and develops a programmable LO signal for the Mixer (MX1) inthe Downconverter/Preamplifier (A1). The frequency of the LO signal is calculated as the sum ofthe visual IF carrier and the visual VHF carrier of the specified output channel. The LO signal'sfrequency is programmed by the setting of switches S1 through S4 which are accessible throughthe module's cover via access holes. The relationship between the setting of these switches andthe resulting LO frequency is provided in Table 2 2 for each VHF channel.A 10MHz reference signal is brought in from the Reference Oscillator (A4A2) through J1, 10MHzIN. Both sections of U4 perform binary divide-by-5 counting to provide a 400kHz signal to theOSCin input of U1, pin 27. To create U1's internal 50kHz reference signal, U1 performs a binarydivide-by-8 operation on the OSCin signal.Controlling the VCO, G1, is the output of op-amp U3. U3 compares and integrates the 0/V and 0/Rphase detector outputs of U1. The output of U3 is filtered to create the dc control voltage for theVCO. The output of G1, RF OUT, is amplified by U5 and available as the Receiver's LO at J2,OUT.The output of G1 is also amplified by U6 and then fed to a ÷64/÷65 prescaler, U2. After prescaling,the signal is connected to U1 pin 1, Fin, from U2 pin 4, OUT, completing the loop. The prescalingfactor of U2 is selected by the MOD CONTROL, pin 9, of U1. Switches S1 to S4 set twodivide-by-ratios, counters A and N, within U1. When divide-by-A is being performed on the signalat Fin, MOD CONTROL is set high, selecting ÷64 in the prescaler, U2. MOD CONTROL goes lowfor divide-by-N selecting ÷65 in U2.The A and N counters form a binary number from A0 to N9 with A0 being the LSB and N9 beingthe MSB. The decimal equivalent of this number, when multiplied by the internal referencefrequency 50kHz, gives the synthesizer's output frequency. Hence, for NTSC operation, A0 andA1, pins 21 and 23 on U1, are grounded. For PAL operation, A0 and A1 are made high by cuttingthe traces from pins 21 and 23 to ground thereby adding the 150kHz to the LO that is characteristicof the PAL system.
2 7When the synthesizer is locked onto a frequency, LD is high. This saturates Q1 and puts a low onSYNTH LOCK. C28 provides a time delay to ensure that the synthesizer has successfully lockedbefore indicating so on the SYNTH LOCK line. For an unlocked condition, LD pulses lowpreventing C28 from charging and saturating Q1. +5V is therefore present on the SYNTH LOCKline for the unlocked condition.2.1j UHF Synthesizer:Schematic Diagram 30367094/Rev B A1A4A110MHz REF. IN (J1) 3.5V P/P square waveLO OUT (J2) +15.25dBm min.SYNTH. LOCK (Pin A of J4) logic high (locked)logic low (unlocked)The UHF Synthesizer is a phase-lock loop type and uses one of the 10MHz reference signals fromthe Reference Oscillator (A4A2) and develops a programmable LO signal for the Mixer in theDownconverter/Preamplifier (A1). The frequency of the LO signal is calculated as the sum of thevisual IF carrier and the visual UHF carrier of the specified output channel. The LO signal'sfrequency is programmed by the setting of switches S1 through S4 which are accessible throughthe module's cover via access holes. The relationship between the setting of these switches andthe resulting LO frequency is provided in Table 2 1 for each UHF channel.A 10MHz reference signal is brought in from the Reference Oscillator (A4A2) through J1, 10MHzIN. Both sections of U4 perform binary divide-by-5 counting to provide a 400kHz signal to theOSCin input of U1, pin 27. To create U1's internal 50kHz reference signal, U1 performs a binarydivide-by-8 operation on the OSCin signal.Controlling the VCO, G1, is the output of op-amp U3. U3 compares and integrates the 0/V and 0/Rphase detector outputs of U1. The output of U3 is filtered to create the dc control voltage for theVCO. The output of G1, RF OUT, is amplified by U5 and available as the Receiver's LO at J2,OUT.The output of G1 is also amplified by U6 and then fed to a ÷64/÷65 prescaler, U2. After prescaling,the signal is connected to U1 pin 1, Fin, from U2 pin 4, OUT, completing the loop. The prescalingfactor of U2 is selected by the MOD CONTROL, pin 9, of U1. Switches S1 to S4 set twodivide-by-ratios, counters A and N, within U1. When divide-by-A is being performed on the signalat Fin, MOD CONTROL is set high, selecting ÷64 in the prescaler, U2. MOD CONTROL goes lowfor divide-by-N selecting ÷65 in U2.The A and N counters form a binary number from A0 to N9 with A0 being the LSB and N9 beingthe MSB. The decimal equivalent of this number, when multiplied by the internal referencefrequency 50kHz, gives the synthesizer's output frequency. Hence, for NTSC operation, A0 andA1, pins 21 and 23 on U1, are grounded. For PAL operation, A0 and A1 are made high by cuttingthe traces from pins 21 and 23 to ground thereby adding the 150kHz to the LO that is characteristicof the PAL system.When the synthesizer is locked onto a frequency, LD is high. This saturates Q1 and puts a low onSYNTH LOCK. C28 provides a time delay to ensure that the synthesizer has successfully lockedbefore indicating so on the SYNTH LOCK line. For an unlocked condition, LD pulses low
2 8preventing C28 from charging and saturating Q1. +5V is therefore present on the SYNTH LOCKline for the unlocked condition.2.1k Downconverter/Preamplifier:Schematic A331-29/Rev B A1A1Gain with Conversion (J1-J2) 3.0dBCollector V (Q1) 7.9VLO Input (Min.) (J3) +7dBmThe Downconverter preamplifier (A1) consists of a single stage, low noise, broadband amplifierwith a double balanced mixer. The VHF or UHF input signal is coupled to Q1 where it is amplifiedbefore driving the mixer. The mixer combines the composite VHF or UHF television signal fromQ1 with a constant amplitude unmodulated RF signal (LO) from the reference oscillator/synthesizerpair or the crystal oscillator/multiplier pair. Both signals are heterodyned in the mixer where theirsum and difference frequencies are developed. Capacitors C10 through C13 along with inductorsL4 through L7 comprise a low-pass filter network allowing only the modulated difference frequency(IF) to pass.2.1l IF SAW Filter/Amplifier:Schematic B331-21/Rev D A1A2Q1 Q2 Q3 J1-J2Gain 21dBCollector V 15V 18V 11VCollector I 16mA 56mA 16mAThe IF Surface Acoustic Wave (SAW) Filter/Amplifier is a three-stage amplifier. TransistorsQ1/Q2 amplify the IF input signal while their associated feedback networks maintain a flatpassband response. The SAW filter provides high selectivity with no need for tuning or alignment.Transistor amplifier Q3 overcomes the loss associated with the SAW filter. Its feedback circuitryis also designed to compensate for nonlinear gain characteristics (i.e., lower gain at the higherfrequencies).
2 92.1m IF AGC Amplifier:Schematic C331-37/Rev G A1A3Q1 Q2 Q3 J1-J2Gain 10-50dBCollector V +20.5Vdc +25Vdc +23.4VdcCollector I 4.5mAdc 27mAdc 60mAdcPower Output 0dBmThe IF AGC Amplifier is a variable gain amplifier with its own automatic gain control and limitersections. The IF AGC Amplifier is calibrated to provide a constant IF output of approximately0dBm with a range of 70dBm to 30dBm received signal. The amplifier section consists of threecommon-emitter RF transistor stages (Q1, Q2, Q3) that produce a combined gain of 50dB.Overall gain is adjustable by varying the amount of Q1's emitter bypass via potentiometer R15(GAIN ADJ). Q2 and Q3 are fixed bias amplifiers separated by a 9dB, 50 ohm-to-50 ohm matchingpad (R22, 23, 24). Q3's feedback network, consisting of TILT ADJ potentiometer R31, inductor L2,and capacitor C12, is designed to compensate for the overall frequency characteristics of themodule (lower gain at higher frequencies). TILT ADJ potentiometer R31 controls the amplifier'sfrequency response by varying the amount of Q3's negative feedback.The automatic gain control section consists of an input AGC circuit (L3, C14, CR8, U1, andsurrounding components) and a variable pin diode attenuator (CR1, 2, 4, and surroundingcomponents). The input AGC circuit is centered around operational amplifier U1. A portion of theIF signal is coupled off of Q3 to a tank circuit (C14, L3) tuned to the visual IF carrier frequency(45.75MHz). The tank energy forward biases detector diode CR8 and then becomes filtered by anRC network (C13, R29) which results in a negative dc voltage proportional to the peak value of thevisual IF signal. This negative dc voltage is buffered by operational amplifier U1B and thensupplied to the Limiter/Output AGC Control (PC1) as the LIMITER REFERENCE OUT voltage.The buffered negative dc voltage is also supplied to operational amplifier U1A where it is invertedand summed with the negative OUTPUT AGC IN reference voltage from PC1, resulting in apositive dc voltage (AGC) proportional to the visual IF signal level. This AGC voltage is used tocontrol the biasing (thus attenuation) of the variable pin diode attenuator and to activate theAutomatic-On circuit (PC2).NOTE: When the front panel OPERATE/ALIGN switch of the Receiver drawer is in the ALIGNposition, the IF AGC Amplifier's PRIMARY AGC OUT voltage is replaced by a +5Vdcreference voltage at pin J3-1.The main function of the limiter circuit is to prevent overdriving the amplifier modules in thetranslator's Upconverter and Power Amplifier drawers when the input signal to the Receiver returnsafter periods of reception fading. For example, following a temporary reduction (fading, etc.) in thereceived signal, the AGC voltage decreases which reduces the attenuation provided by the IF AGCAmplifier's variable pin diode attenuator. However, once the received signal regains its strength,the variable pin diode attenuator cannot attenuate this signal fast enough. The limiter circuit isused to overcome this characteristic of the variable pin diode attenuator. Notice that with anincrease in the received signal, the AGC voltage increases while the limiter reference voltagedecreases. The variable pin diode attenuator will eventually respond to the increase in the AGCvoltage by increasing its attenuation. The limiter control circuit on PC1 quickly responds to a 3dBor greater instantaneous increase in the IF AGC Amplifier's LIMITER REFERENCE OUT voltageJ3-3 by pulling the LIMITER ENABLE IN J3-4 low, turning off transistor Q4 of the IF AGC Amplifier.
210With Q4 turned off, the dc forward bias is removed from pin diode CR9, thus reducing momentarilythe IF output of the IF AGC Amplifier by approximately 20dB. The momentary attenuation in theIF output by the limiter circuit allows sufficient time for the variable pin diode attenuator to adjustitself to the change in the AGC voltage. Overdriving can also occur when the translator is firstturned on. To compensate, Q6 is on, turning on Q5. This shuts off Q4, increasing the attenuationof CR9, as above, until C32 charges. Q6 and Q5 then turn off, allowing LIMITER ENABLE IN,which is normally high, to turn on Q4. This forward biases CR9 by providing a dc path to groundthrough it for the +15V from pin J3-5.2.1n Automatic-On:Schematic B331-44/Rev C A1PC2The Automatic-On circuit uses differential amplifier U1A to compare the AGC voltage, developedby the IF AGC Amplifier, to a preset reference voltage set by THRESHOLD ADJUST potentiometerR4. An input signal above the minimum acceptable Receiver input level of 60dBm will producean AGC voltage above the Auto-On Threshold potential. As the AGC voltage (pin 3 of U1A)exceeds the Auto-On Threshold reference voltage (pin 2 of U1A), differential amplifier U1Asaturates in the positive mode charging capacitor C1. Once C1 charges above the referencepotential at pin 6 of U18, differential amplifier U1B will also saturate in the positive mode turningon transistor Q1. With Q1 forward biased, a ground is provided for relay K1 which energizes thedevice. The closed contacts of K1 place +5Vdc on the INTLK (VIDEO SENSE) line going to theExciter’s Control Board (A2PC1). An Auto-On delay network consisting of R8, R9, and C1 slowsdown the turn-on and turn-off activation time. This delay of approximately 30 seconds preventson/off cycling from occurring during periods of weak reception lasting for less than 30 seconds.2.1o Limiter/Output AGC Control:Schematic B331-34/Rev C A1PC1 The Limiter/Output AGC Control board monitors and controls the IF AGC Amplifier (A3) andcontrols the CARRIER PRESENT LED (DS1) on the Receiver front panel.The AGC negative reference voltage is placed on pin 3, OUTPUT AGC, by inverting op-amp U1B.Potentiometer R9, AGC REF, sets this voltage. Keep the PRE AGC REF ADJ potentiometer fullyclockwise because it and the POWER REFERENCE portion of the AGC circuit, from pin 1 to pin 2,are not used in this application.LIMITER REFERENCE IN is brought in from A3 on pin 12 and is compared to an 11.8V referenceby U2B. When a carrier greater than 60dB is received, the output of U2B will saturate byapproximately +15V turning on Q3. This provides a path to ground through current limiting resistorR23 on pin 10 for the CARRIER PRESENT LED (DS1) on the Receiver drawer front panel,illuminating it green. If the received carrier level drops below 60dBm, U2B saturates to 15Vturning off Q3. The LIMITER ADJUST potentiometer, R13, voltage divides the LIMITERREFERENCE INPUT and passes it through unity gain follower U2A and unity gain follower U2C.U2D takes the difference between the 8.7V reference, from CR2, and the output U2C. For thenominal level of the carrier being received, the output of U2C is less than 8.7V and U2D putsapproximately +15V on LIMITER ENABLE OUT, pin 9. The LIMITER ADJ is set so that, if
211LIMITER REFERENCE IN increases by 3dB, the output of U2C will be greater than 8.7V and U2Dwill saturate to approximately 15V pulling down LIMITER ENABLE OUT.2.1p Aural Notch Filter:Schematic Diagram 10383097/Rev 51 A1FL2Insertion Loss (J1-J2) 0.4dB Max.The Aural Notch Filter provides a means of attenuating the aural carrier 3dB which can be usefulfor reducing the effects of in-band and out-of-band intermodulation. Variable capacitor C3 tunesthe notch to the aural IF frequency in an NTSC system, 41.25MHz. This capacitor is preset by theEMCEE Test Department. R1 sets the amount of attenuation; up to 3.5dB of attenuation can beattained. The filter is a very high Q type and does not have an appreciable effect on the visualcarrier or color subcarrier.2.1q Multi-Output Power Supply:Interconnection Diagram B326-18/Rev C A1PS1Voltage Rated Current+25Vdc 1Adc±15Vdc 1Adc±5Vdc 1AdcAs shown on the Interconnection Diagram, the Multioutput Power Supply consists of surgesuppressor E1, transformer T1, and printed circuit boards PC1 and PC2. PC1 is the +25V PowerSupply, and PC2 is the ±15V/±5V Power Supply. Surge suppressor E1 provides voltage-transientprotection for the step-down transformer T1 and the +25V Power Supply.+25V Power Supply:Schematic B326-15/Rev C A1PS1PC1The secondary voltage of step-down transformer A1PS1T1 is applied to bridge rectifier CR1. Afterfiltering, the rectified voltage ( 36V) is regulated by U1 to the +25Vdc level. The output voltageof U1 is fixed by resistors R1, R2, and R3. +25Vdc is supplied to various modules in the Receiverdrawer.
212±15V/±5V Power Supply:Schematic B326-12/Rev D A1PS1PC2120Vac is placed across the primary of step-down transformer T1. Surge suppressor E1 providesvoltage-transient protection for this supply. Transformer T1 supplies a secondary voltage to bridgerectifier CR1. The output of CR1 is divided, with the negative voltage applied to 15Vdc regulatorU2 and the positive potential fed to +15Vdc regulator U1. Voltage regulators U3 and U4 tap off ofthe 15V lines to provide +5Vdc and 5Vdc, respectively. The capacitors provide filtering for thedifferent regulators. ±15Vdc is supplied to the IF AGC Amplifier (A3), the Limiter/Output AGCcircuit (PC1), and the Automatic-On circuit (PC2). +5Vdc is supplied to the IF AGC Amplifier (A3).2.1r Digital Code ID Unit: (OPTIONAL)Schematic 20258029/Rev A A1PC3According to FCC Rules and Regulations, Section 74.783, each television broadcast transmitterin the United States of over 1 watt peak visual power must transmit its call sign in InternationalMorse Code every 60 minutes or arrange for the primary station to visually or aurally identify thetransmitter and its location. The Digital Code Identification Unit is available for the customer whowishes to identify a transmitter station with Morse Code. The ID unit is a sixteen word by eight bitsequencer which generates a series of pulses used to shift the frequency of the transmitted carriersby frequency shift keying (FSK) the transmitter's Upconverter Oscillator.The Digital Code ID Unit is composed of four integrated circuits: a Dual Timer (U4), a Dual 4 BitCounter (U3), a Programmable Read Only Memory (U2) and an 8 to 1 Line Multiplex (U1). TheDual Timer or master clock contains two sections which control the operation of the ID unit bydictating when and at what rate pulses will be fed to the Upconverter oscillator. The first sectionof the timer is a gated astable oscillator or bit clock which produces square-wave pulses at a rateof approximately 20Hz. The bit rate is controlled by U4 resistors R11, R12 and capacitor C2. Thesecond section of U4 is a 20 minute timer controlled by resistors R9, R10 and capacitor C1. WhenC1 charges to 63% of its capacity (after 20 minutes), pin 9 of U4 will go low, reverse biasingtransistor Q3 which presents a high (4Vdc) at pin 4. This high gates on the bit generator whichfeeds the 20Hz pulses to pin 1 of the Dual 4 Bit Counter (U3).As each clock pulse reaches pin 1 of U3, the 4 Bit Counter "counts" the number of pulses enteringthe chip and displays that count in binary code at its own pins 3, 4 and 5. For example, as the firstpulse is fed to U3, pin 3 goes high representing the decimal number 1 in binary code (001). Withthe second clock pulse, U3 pin 4 goes high and pin 3 goes low representing the binary number 2(010). This counting process will continue up to the number 7 (111) and, as the eighth pulse is fedto the counter, pins 3, 4, and 5 will all go low (000) to begin the sequence over again. During thistime integrated circuit U2, the Programmable Read Only Memory (PROM), has a series of high andlow voltages present at its pins 1 through 9 (excluding pin 8 which is ground). These voltages arebits which make up the first word (Morse code letters or numbers) of the transmitter's call sign.(The transmitter's call sign is programmed into the PROM by the EMCEE test department.) Inorder for this information to be delivered to the Upconverter oscillator, it must be converted fromparallel form to serial form by the 8 Line to 1 Line Multiplexer (U1). The binary numbers developedby the Dual 4 Bit Counter are fed to pins 9, 10, and 11 of the 8 to 1 Line Multiplexer. Each binarynumber (or voltage fluctuation) presented to U1 signals the multiplexer circuit to individually read(take) the parallel bits presented by the PROM and deliver them serially to the oscillator viatransistor Q4. Therefore, as the Dual 4 Bit Counter (U3) feeds the binary numbers 1 (001) to pins
2139, 10 and 11 of the Line Multiplexer (bit address), the Multiplexer reads the bit at pin 1 of thePROM (U2) and delivers it to the base of transistor Q4. With each subsequent binary number(010, 011, 100, 101, 110, 111, 000) provided by the Dual Counter, the Line Multiplexer will readeach individual PROM bit present at U2 pins 2 through 9 (exclude pin 8) until the Dual Counterreaches 111. The next pulse then resets the count to 0 (000). The transition from high to low (1to 0) at pin 5 of the counter is seen by pin 13, causing pin 11 of U3 to go high. This binarynumber 1 (0001) seen by pins 10, 11, 12 and 13 (word address) of U2 causes the PROM to presentthe second set (word) of eight bits to the Line Multiplexer. The Dual Counter (U3 – pins 3, 4, 5)presents another binary eight count to the Line Multiplexer (U1 – pins 9, 10, 11) which individuallyreads the eight new PROM bits (U2 – pins 1 through 9) and delivers them to transistor Q4. At theend of the second eight count, pin 13 of U3 again sees a high to low transition which causes pin 10of U3 to go high while pin 11 goes low (binary number 2 = 0010). With U2 pins 10 through 13receiving a binary number 2, a third word is presented to the Line Multiplexer by the PROM. Thisentire process occurs so that the PROM delivers 16, eight bit words to the Upconverter oscillatorvia the Line Multiplexer. After word 16, pins 8 through 10 of U3, which were all high (binarynumber 16 = 1111), drop to zero. The negative going transition at pin 8 of U3 is coupled totransistor Q1 via C3. This action forward biases transistor Q2 which discharges capacitor C1. Asthe voltage at pin 12 of the Dual Timer drops, pin 9 goes high causing pin 4 of U4 to go low. TheDual Timer's bit clock is gated off, disabling the Digital Code Identification Unit for 20 minutes untilcapacitor C1 recharges.2.2 Exciter/Upconverter Drawer:Interconnection Diagram 40383113/Rev 55 A2 TTU20FComposite IF IN (J1) 8dBm peak visualRF OUT (J2) +43dBm peak visual+33dBm average auralLO SAMPLE (J3) +9dBm ± 2dBmThe Exciter/Upconverter drawer converts the composite IF signal from the Receiver to the desiredUHF channel, then amplifies the RF signal to the desired output level. This drawer is used to drivethe two Dual 300W Final Amplifier Drawers (A3, A4). The Linearizer provides precorrection to thecomposite IF signal. Upconversion is performed by the IF Upconverter (A1) along with the UHFSynthesizer (A4). The UHF Synthesizer provides a programmable LO to the IF Upconvertermodule where the LO and IF signal from the Receiver are mixed to create the desired UHFfrequency. The IF Upconverter also provides AGC and precorrector functions. The UHF signalfrom the Upconverter module is passed through a UHF Bandpass Filter (FL1) to remove theunwanted products from the conversion process while passing the desired signal with a minimalloss. The RF is then amplified approximately 50dB by a 2W Driver Amplifier (A2) and thenamplified another 12dB by a 20W UHF Amplifier (A3). The output signal is passed through theMetering Coupler (DC1). The Metering Coupler provides samples for the Metering Detector (A5)while passing the signal to the output of the drawer.Metering and control functions are provided by the Metering Detector, the Metering Switch (PC2),and the Control Board (PC1). The Control Board also has several status and diagnostic LEDindicators. Power is supplied to the drawer by two power supplies, a ±15V/+5V linear supply (PS2)and a +28V switching supply (PS1).
2142.2a Linearizer:Schematic Diagram 30367078/Rev 60 A2A6Gain with S1 OFF (J1-J2) 3dB min./6dB max.Gain with S1 ON (J1-J2) 6dB min./12dB max.Emitter of Q1/Q2 +4.8Vdc @ 13mAdc/+13Vdc @ 30mAdcEmitter of Q3/Q4 +3.3Vdc @ 11mAdc/+15Vdc @ 45mAdcEmitter of Q5 +8.7Vdc @ 22mAdcThe Linearizer is a five-stage circuit which compensates for linearity distortions generated by thetranslator's Class AB power amplifiers. Transistors Q1 through Q5 are all amplifier stages with theQ1/Q2 combination providing approximately 20dB of gain. 8dB of gain is provided by transistorsQ3/Q4. Q2, Q4, and Q5 are used as low impedance emitter followers. Variable gain expansionnetworks which furnish linearity correction are centered around diodes CR1 through CR8, slopepotentiometers SL1 through SL4 (i.e., R10, R11, R21, R22), unity gain inverting amplifiers U1 andU2, threshold potentiometers TH1 through TH4 (i.e., R37, R38, R39, R40), and switch S1. WhenS1 is in the OFF position, each diode pair is continuously reverse biased throughout the positiveand negative cycles of the visual IF carrier. Due to the high reverse resistance provided by CR1through CR8, each network essentially represents a resistive L-pad with the composite IF signalattenuated by a fixed amount. As a result, no linearity correction is provided. However, when S1is in the ON position and the Linearizer is properly adjusted, the four diode pairs form a nonlinearcircuit where each diode pair is biased to turn on at different points of the positive and negativecycles of the visual IF carrier envelope. Each diode pair is initially reverse biased by equal butopposite polarity dc voltages established by U1 and U2. L1 through L8, shunted by R29 throughR36, isolate the visual IF carrier from the diode biasing circuitry. When the positive and negativepeaks of the visual IF carrier are sufficient to forward bias a diode pair, the diode pair turns onplacing the resistance of its respective slope potentiometer either in parallel or in shunt to groundwith its respective series arm resistance. As a result of switching additional resistance in parallelor shunt with the series arm of the L-pad, the attenuation of the visual IF carrier is reduced.Threshold potentiometers TH1 through TH4 determine the turn-on point of each diode pair whileslope potentiometers SL1 through SL4 vary the amount of gain expansion achieved during theturn-on period of each diode pair. Threshold controls TH1, TH2, and TH3 are used to adjust thedifferential gain of the white to black region while TH4 adjusts the sync amplitude. When properlyadjusted, the Linearizer provides sync amplitude, differential gain, and intermodulation correctionto the RF output signal.2.2b IF/Upconverter:Schematic Diagram 30383013/Rev 55 A2A1IF INPUT (J1) 8dBm peak visualRF OUTPUT (J2) 13.5dBm minimumLO SAMPLE (J3) +9dBm ± 2dBLO INPUT (J4) +13dBm minimumThe IF/Upconverter performs three tasks in this translator. It provides signal precorrection, AGClevel control, and it upconverts the IF signal to the desired UHF channel. This module alsoprovides a sample of the LO signal to the Exciter’s front panel.
215The IF input at J1 is attenuated by AT1, an adjustable attenuator which can be tuned tocompensate for different input levels. A monolithic amplifier (U1) provides approximately 12dBof gain to the signal passed through the attenuator. U1 is biased by R1 with L1 providingimpedance matching and isolation. C2 is an RF bypass capacitor, while C1 and C3 are couplingcapacitors. T1 steps up the signal's voltage to drive the precorrector circuit made up of CR1, C4to C6, C8 to C12, R2 through R10, L4, L5, U2, and S1. This circuit compensates for linearitydistortions generated by the wideband power amplifiers or created by the Receiver. When switchS1 is in the off position (open), this circuit reduces to a simple attenuator formed by R2 and R3;therefore, no precorrection is provided. When S1 is on, the precorrector becomes a nonlinearcircuit that provides less attenuation for the positive and negative peaks of the IF signal, therebystretching the waveform. CR1 is biased by U2 A and B, with each op amp biasing one half of CR1.The amount of bias provided by U2 is determined by R7 through R10. R9 allows the bias level tobe adjusted. This adjustment determines at which point on the waveform precorrection begins.R5, R6, C8 through C11, L4, and L5 provide isolation between CR1 and U2. C4 to C6 are dcblocking capacitors. The precorrector operates by placing R4 in parallel with R2 when the IF signalis positive or negative enough to forward bias half of CR1. Adjusting R4 determines the amountof precorrection provided. At the output of the precorrector, a second monolithic amplifier provides+12dB of gain to the IF signal. C7 and C14 are coupling capacitors while C13 acts as an RFbypass. L2 is an RF choke and R11 provides the correct bias voltage for U3.The next circuit in the Upconverter is the AGC circuit. Three PIN diodes, CR2, CR3, and CR4,form a voltage controlled attenuator along with R14 and C17. C14, C16, and C18 serve as dcblocking capacitors. Bias is provided to this attenuator by R12, VR1, and R13, as well as R15, L3,and the three operational amplifiers U4(A), U5(A), and U5(B). C15, C32, and C19 are bypasses.The control voltage for the AGC is generated by U5(B). A dc voltage proportional to the outputpower is connected to pin 6 of U5 by R26. A reference voltage from the Control Board's PowerAdjust circuit is supplied to pin 5 of U5 by R22. U5(B) compares these two voltages and providesa control voltage at pin 7 of U5. R27 sets the gain of U5(B) to unity. U5(A) is an integrator thatprovides a smooth transition for the changing control voltage. Input to U5(A) is provided by R20,with C22 as the integration capacitor. A reference voltage is provided to pin 3 of U5 by R21 andCR5 through CR7. The output of U5(A) is passed through an attenuator formed by R18 and R19before driving the unity gain buffer amplifier formed by U4(A) R16 and R17. When the OPERATE/ALIGN switch is in the ALIGN position, pin 3 of U4A is grounded. This defeats the AGC circuit andallows minimum attenuation of the IF signal. Q1, R35-R37 and C33 make up a soft start circuitthat retards the spike in output power that normally would occur when the translator is turned ONand the OPERATE/STANDBY switch is placed in the OPERATE position. The circuit placesapproximately +13Vdc on pin 3 of U4A, putting the AGC circuit into a condition of maximumattenuation. As C33 charges, this imposed voltage on pin 3 decreases giving the AGC circuit timeto stabilize before Q1 turns off and the output of U5A takes control of the AGC. Whenever +28Vswitched is removed from the drawer (OFF or STANDBY), CR8 forward biases and C33 dischargesthrough it and R38 to ground. The output of U4(A) is the AGC control voltage.The IF output of the AGC circuit connects to mixer MX1 where it is combined with the LO signalfrom the synthesizer to produce the desired UHF channel frequency at the RF output port, J2. TheLO is brought to the mixer by R29 and R30 (which provide isolation) and U7, an amplifier thatprovides about 12dB of gain to the signal. U7 is biased by R28. A sample of the LO is alsosupplied to connector J3 via U6, the input of which is attenuated by R31 to R33. U6, biased byR34, provides 12dB of gain. C24 to C27 are coupling capacitors, while all remaining capacitorsare RF bypasses.
2162.2c UHF Synthesizer:Schematic Diagram 30367094/Rev B A2A4A110MHz REF. IN (J1) 3.5V P/P square waveLO OUT (J2) +15.25dBm min.SYNTH. LOCK (Pin A of J4) logic high (locked)logic low (unlocked)The UHF Synthesizer is a phase-lock loop type and uses one of the 10MHz reference signals fromthe Reference Oscillator (A4A2) and develops a programmable LO signal for the Mixer (MX1) inthe IF Upconverter (A1). The frequency of the LO signal is calculated as the sum of the visual IFcarrier and the visual UHF carrier of the specified output channel. The LO signal's frequency isprogrammed by the setting of switches S1 through S4 which are accessible through the module'scover via access holes. The relationship between the setting of these switches and the resultingLO frequency is provided in Table 2 1 for each UHF channel.A 10MHz reference signal is brought in from the Reference Oscillator (A4A2) through J1, 10MHzIN. Both sections of U4 perform binary divide-by-5 counting to provide a 400kHz signal to theOSCin input of U1, pin 27. To create U1's internal 50kHz reference signal, U1 performs a binarydivide-by-8 operation on the OSCin signal.Controlling the VCO, G1, is the output of op-amp U3. U3 compares and integrates the 0/V and 0/Rphase detector outputs of U1. The output of U3 is filtered to create the dc control voltage for theVCO. The output of G1, RF OUT, is amplified by U5 and available as the Exciter/Upconverter'sLO at J2, OUT.The output of G1 is also amplified by U6 and then fed to a ÷64/÷65 prescaler, U2. After prescaling,the signal is connected to U1 pin 1, Fin, from U2 pin 4, OUT, completing the loop. The prescalingfactor of U2 is selected by the MOD CONTROL, pin 9, of U1. Switches S1 to S4 set twodivide-by-ratios, counters A and N, within U1. When divide-by-A is being performed on the signalat Fin, MOD CONTROL is set high, selecting ÷64 in the prescaler, U2. MOD CONTROL goes lowfor divide-by-N selecting ÷65 in U2.The A and N counters form a binary number from A0 to N9 with A0 being the LSB and N9 beingthe MSB. The decimal equivalent of this number, when multiplied by the internal referencefrequency 50kHz, gives the synthesizer's output frequency. Hence, for NTSC operation, A0 andA1, pins 21 and 23 on U1, are grounded. For PAL operation, A0 and A1 are made high by cuttingthe traces from pins 21 and 23 to ground thereby adding the 150kHz to the LO that is characteristicof the PAL system.When the synthesizer is locked onto a frequency, LD is high. This saturates Q1 and puts a low onSYNTH LOCK. C28 provides a time delay to ensure that the synthesizer has successfully lockedbefore indicating so on the SYNTH LOCK line. For an unlocked condition, LD pulses lowpreventing C28 from charging and saturating Q1. +5V is therefore present on the SYNTH LOCKline for the unlocked condition.
2172.2d Reference Oscillator:Schematic Diagram 10368037/Rev B A2A4A210MHz REF. OUT (J1, J2) 3.5V P/P square waveThe Reference Oscillator provides a 10MHz reference signal for the UHF Synthesizer (A4A1). Thismodule is centered around a 10MHz temperature-compensated crystal oscillator (G1). The outputfrom G1 is applied to two exclusive-OR gates used as inverting buffers. The output signal fromeach gate is a 10MHz low-level square wave with a frequency stability of 0.3 parts per million(PPM).2.2e UHF Bandpass Filter:Schematic Diagram 10331209/Rev 52 A2FL11dB Bandwidth (J1-J2) 7MHzInsertion Loss (J1-J2) 3dB Max.The UHF Bandpass Filter (FL1) consists of three tunable resonant cavities, with the three tuningcapacitors of the filter adjusted to provide the frequency response, shown in Figure 3 5, selectingthe appropriate UHF channel. FL1 is tuned to select the desired UHF mixer products from thelower sideband or difference signal found at the RF OUTput (J2) of the IF/Upconverter (A1)module.2.2f 2W UHF Amplifier:Schematic Diagram 30367002/Rev A A2A2Gain (J1-J2) 50dBPower Output +33dBm peak visual+23dBm average auralFlatness (J1-J2) ±1dB from 470-860MHzU1, PIN 3 +3.9Vdc @ 29mAU2, PIN 3 +5.3Vdc @ 58mAU3, PIN 4 +20Vdc @ 100mAQ1, Collector +25Vdc @ 600mAThe 2W UHF Amplifier (A2) provides amplification to the selected UHF channel. The Amplifier isa four-stage, class A, microstrip design. The first three stages are centered around broadbandmonolithic amplifiers U1 through U3 which provide a combined gain of 40dB. The fourth stage isan RF transistor amplifier Q1 which provides a gain of approximately 10dB. Q1 is biased by a dccurrent regulator consisting of Q2, R4, R5, R6, R7, and R9. This circuit continuously maintains thecollector voltage and current of Q1 over a wide variation of load and temperature. The requiredcollector voltage and current of Q1 is established by potentiometer R5. Input matching for Q1 isprovided by C9, C10, C11, C12, and C24 while output matching is accomplished by C13, C14 andC30. Capacitor C10 is tuned for maximum gain with a flat frequency response from 470 to860MHz. C1, C3, C5, C8, and C14 provide signal coupling while all other capacitors are used for
218bypassing. Coils L1 through L4 function as RF chokes while R1 through R3 are used as biasingresistors.2.2g 20W UHF Amplifier:Schematic Diagram 40383053/Rev 52 A2A3Gain (J1-J2) 12dB min.Power Output +44.5dBm peak visual/+34.5dBm average auralFlatness (J1-J2) ±1dB from 470-860MHzCollector of Q1 & Q2 +26.8Vdc @ 1.2Adc (each side)The 20W UHF Amplifier is a class A, broadband, microstrip design consisting of two RF transistorstages centered around push-pull devices Q1 and Q2. These two stages are connected in parallelvia splitter CP1 and combiner CP2. Q1 and Q2 are biased by separate dc current regulators whichcontinuously maintain each collector voltage and current, over a wide variation of temperature andsignal level. Each current regulator is made up of PNP transistors Q3 and Q4 working withpotentiometers R4 and R11 to provide the required collector voltage and current for each side ofQ1 and Q2. CP1 and CP2 are Wireline quadrature 3dB,90 hybrid couplers which split andcombine power equally with resistors R5/R12 used to terminate the isolated port of each. Thefunction of R5/R12 is to absorb any imbalance that develops in either hybrid as well as to establisha 50 ohm input/output impedance. Baluns Z1/Z3 transform the unbalanced signal into a balancedinput to drive the push-pull transistor pair of Q1/Q2. Baluns Z2/Z4 act in the opposite manner totransform the balanced output from Q1/Q2 into an unbalanced output. Input matching fortransistors Q1/Q2 is provided by capacitors C1-3, C32, C65, C76/C18-C21, C66, C77, C80 whileoutput matching is accomplished by capacitors C43, C68-C70, C72, C81/C48, C53-C55, C74, C82.Variable capacitors C79, C32, C80, and C18 are tuned for maximum gain with a flat frequencyresponse. Coils L1 through L8 function as RF chokes while capacitors C1, C2, C20, C21, C68,C69, C54 and C55 are used for signal coupling. All other capacitors are used for bypassing.Fault Circuit:The Fault Circuit board (PC3) detects the presence of either an open or shorted RF device in the20W UHF Amplifier. Under normal operation, the collector voltage on both sides of each push-pulltransistor in the 20W UHF Amplifier is typically +26.8Vdc. Under this condition, Q1 through Q3of the fault circuit are turned on, the diodes identified by pins 1 and 3 in CR2 and CR3 are turnedon, the diodes identified by pins 2 and 3 are turned off, and the diodes identified by pins 1/14 and7/8 of CR1 are turned on while those identified by pins 2/13 and 3/12 are turned off. Hence, fornormal operation of each push-pull RF transistor, the FAULT line (pin C of connector J3) is set ata logic low (approximately 0Vdc) by the pull-down resistor (R10) or the Control Board (A2PC1).However, if either side of one of the push-pull transistors opens, its collector voltage rises from+26.8Vdc to about +27.4Vdc. This action results in turning off Q3 and Q2 as well as the diodeidentified by pins 7 and 8 of CR1. With these components turned off, the diode identified by pins3 and 12 of CR1 turns on applying a logic high (approximately +4.7Vdc) to the FAULT line. On theother hand, if either side of one of the push-pull transistors shorts, the shorted transistor collectorfalls from +26.8Vdc to about +0.2Vdc causing the diode identified by pins 2 and 3 of either CR2or CR3 to turn on. This action results in turning off Q1 and the diode identified by pins 1 and 14of CR1. With these components turned off, the diode identified by pins 2 and 13 of CR1 turns on
219applying a logic high to the FAULT line. The information on the FAULT line is processed by thefault monitoring/display section of the Control board (A2PC1).2.2h Metering Coupler:Schematic Diagram 10199178/Rev 52 A2DC1Insertion Loss (J1-J2) <0.5dBFWD Coupling (J1-J3) 30dBREFL Coupling (J1-J4) 30dBThe Metering Coupler is a four-port device designed to provide forward and reflected RF samplesto the Metering Detector (A5) with minimal loss to the output signal. The RF signal is applied tothe coupler's input port (J1) and exits the coupler with a maximum of 0.5dB of loss at J2. A 30dBsample of the signal's forward power is provided at J3, and a 30dB sample of the reflected poweris provided at J4. These two signals are connected to the Metering Detector (A5) which thenprovides DC signals proportional to the output signal to the Control Board (PC1), the AGC circuits,and the Metering Switch (PC2).2.2i Metering Detector:Schematic Diagram 30368024/Rev P A2A5The Metering Detector contains three circuits for monitoring signal levels. Each of these circuitscan take an RF signal at its input and provide a DC voltage at its output proportional to the inputsignal's strength. Only two of the detector circuits are used in this application. A sample of theoutput signal is supplied to the VISual port of the detector, and a sample of the reflected power isprovided at the REFLected input of the detector. These signals are provided by the MeteringCoupler (DC1). The front end or detector portion of each circuit is basically the same. Diodes CR2and CR4, together with their surrounding components, convert the sampled on-channel RF signalsto positive dc voltages proportional to the detected RF power. Detection of the sampled visualoutput carrier is accomplished by CR2 in conjunction with R4 and C2 which form a time constantof 1 second. R4 is the dc load while C1 and C11 form the RF ground of the visual power detector.Detection of the sampled reflected signal is the same except for a faster time constant. R22/C6forms a time constant of 1 millisecond. The positive dc voltages from the visual and reflectedpower detectors are processed by buffer amplifiers U1 and U2 which provide voltage gains of 1V/Vand 2V/V, respectively. These buffer amplifiers also provide isolation between the % POWERmeter and the detectors. The settings of potentiometers R9 and R27 determine the voltage levelapplied to the % POWER meter when the meter switch (PC2) is in its FWD or REFL positions,respectively. The aural detector circuit is not used in this application.A dc voltage proportional to the Exciter's output power is available at pin 5 of connector J4,designated VISUAL POWER REFERENCE.
2202.2j Control Board:Schematic Diagram 40383016/Rev 62 A2PC1The Exciter’s Control Board (PC1) is mounted to the inside of the Exciter/Upconverter's front panel.It provides various monitoring and control functions for the Exciter while displaying the results onfront panel indicators and the metering display. The circuitry can be divided into three sections:(1) Interlock Monitoring/Display(2) Amplifier Fault Monitoring/Display(3) Miscellaneous Control/DisplayThe Interlock section monitors the VIDEO SENSE from the modulator (optional), SYNTH LOCK,the 20W amplifier TEMP SENSOR, VSWR OVLD, the +28V FINAL PS and OPERATE/STANDBYswitch. When these signals are of the appropriate level with the OPERATE/STANDBY switch setto OPERATE and the POWER circuit breaker ON, the contactor (K1) closes placing the translatoron line. The FINAL BIAS, ON and SYNTH LOCK indicators are now illuminated green and theTEMP EXCITER and VSWR OVLD indicators are unlit when the interlock is closed.With baseband video present, the optional VIDEO SENSE line (J1-3) from the modulator is high.The SYNTH LOCK line at J1-8 is low when the synthesizer is locked on frequency. This forces theoutputs of U1D and U1F high. U1F saturates Q9, illuminating the SYNTH LOCK LED (DS5) green.If video is lost, the VIDEO SENSE line will go low. An unlocked synthesizer puts a high on theSYNTH LOCK line causing the outputs of U1D and U1F to go low and Q9 to cut off, extinguishingDS5. Should either of these situations occur, the output of U3A, which is normally high, will bedriven low. Note that the VIDEO SENSE line can be left unconnected and R30 will hold it high sothat the translator will operate.The 20 WATT TEMP SENSOR line (J1-7) connects to ground through thermostat S1 mounted tothe heat sink of the 20 Watt UHF Amplifier, A3. When the temperature of the thermostat is below150 F, the thermostat is closed. This pulls the 20 WATT TEMP SENSOR line low, driving inverterU1H high and buffer U2H low. Temperatures in excess of 150 F cause the thermostat to open andthe 20 WATT TEMP SENSOR line goes high. This high drives U1H low and U2H high shuttingtransistor Q8 off and extinguishing TEMP EXCITER LED DS4. DS4 is illuminated yellow whenU2H is forced high causing Q8 to conduct.The FINAL AMPL TEMP SENSOR line (J1-24) in the Exciter monitors the momentary (10 second)VSWR OVLD signal from the main Control Board (A5PC1)mounted behind the Front Panel (A5)at the top of the translator cabinet. This line is normally low, driving U1B high and reverse biasingCR1. When a VSWR OVLD occurs at the output of the translator, a high is present at J1-24 drivingU1B low. A low at the output of U1H or U1B forward biases CR1 or CR4, respectively, and placesa low on pin 5 of U3B which is normally high.The final VSWR OVLD signal from the main Control Board (A5PC1) is applied to pin J1-5. Undernormal operation with the forward and reflected powers correctly set, this line is low. This turns Q1off and Q2 on. U4A is set to have a high at Q/pin 6, and a low at Q/pin 5. The low at pin 5 turnsoff Q5 and the red VSWR OVLD indicator (DS7). If the reflected power exceeds the referencelevel set in the translator’s output Metering Detector (A5A7), the VSWR OVLD line goes high,turning on Q1 and providing a discharge path for C11. C11, R22, and CR2 provide a quick on/slow off circuit so that a transient does not trigger the VSWR OVLD circuit. When C11 hasdischarged sufficiently, Q2 will shut off. This causes the CLK input, pin 3, of U4A to go from lowto high triggering the flip-flop action of U4A. Q is now high turning on Q5 and the red section ofDS7. Q is now low and places a low at pin 4 of U3B. The VSWR OVLD line returns to
221approximately 0.6Vdc when this occurs. The Exciter’s momentary VSWR RESET switch (S2)resets U4A by grounding the CLR input/pin 1 when depressed. The REMOTE VSWR OVLDRESET (J1-21) allows the VSWR overload circuit to be reset from a remote location through theREMOTE MONITOR jack J4.The output of U3B is normally high; however, if a low appears at either input of U3B, its output willbe driven low. The output of U3B connects to one input of U3D while the output of U3A connectsto the other input through the OPERATE/STANDBY switch. Under normal operating conditions,the output of U3D is also high. If U3A goes low while S1 is in the OPERATE (closed) or STANDBY(open) position or if U3B goes low, the output of U3D will be pulled low. When U3D is high, Q6 andthe green section of the FINAL BIAS indicator (DS6) are turned on, Q3 is off and the FINAL PSINHIBIT line at J1-4 is floating. If U3D goes low, Q6 and DS6 turn off while Q3 turns on, groundingthe FINAL PS INHIBIT line which shuts down the power supplies of each 300 Watt UHF PowerAmplifier placing the translator in standby.The output of U3C is normally high with U3D connected to one input of U3C. RF DRIVECONTROL J1-9 will also be high provided that all the +28V Power Supplies (A3PS1, A3PS2,A4PS1, A4PS2) contained in the Dual 300W UHF Power Amplifier drawers are functioningproperly. If this is not the case or if U3D goes low, U3C will trip low turning off transistors Q7, Q4and the ON indicator (DS8). With Q4 off, ground is removed from the CONTACTOR CONTROLline (J1-11) and it is left floating. This deenergizes the contactor and removes +28V from the IFUpconverter (A1), the 2 Watt UHF Amplifier (A2) and the 20 Watt UHF Amplifier (A3). Duringnormal operation U3C is high, turning on transistors Q7, Q4 and the green portion of LED DS8. The CONTACTOR CONTROL line is pulled to ground through Q4. (Note that J1-9 cannot be leftunconnected or U3C will never go high.) Once the output of U3C goes low, it will remain in thatstate until the condition which caused the low at either of U3C's inputs is corrected.The Amplifier Fault Monitoring/Display section monitors the 20W AMPL FAULT line (J1-13) whichis low when the 20 WATT UHF AMPLIFIER module (A3) is functioning properly. A fault isrepresented by a high on the line. For normal operation of the 20 WATT UHF AMPLIFIER, U1Eis high illuminating the green section of the DRIVER AMP indicator (DS1). At the same time, U2Eis low bypassing the red section of DS1. For a fault, the opposite occurs. U1E goes lowextinguishing the green section of DS1 and U2E goes high illuminating the red section of DS1.There are three Miscellaneous Control/Display circuits. The POWER ADJUST potentiometer,which is accessible through the front panel of the Exciter, sends a DC voltage to the AGC circuitin the IF Upconverter (A1) to control the final output power of the translator. The OPERATE/ALIGN switch engages or defeats the AGC circuit. In the ALIGN position, J1-23 is grounded andthe OPERATE indicator (DS9) is unlit. In the OPERATE position DS9 is illuminated green and theOP/ALIGN line is an open circuit on the Control Board. The voltage on the METER line (J1-15)is selected by the METERING SWITCH (PC2) mounted below the 30-segment LED bar graphdisplay on the front panel. Forward power (FWD), reflected power (REFL), +28V or +5V meterindications can be chosen. The voltage level is decoded by three voltage level-indicator drivers(U5-U7) and the appropriate number of LEDs are lit on the bar graph display (DS10-DS12).
2222.2k Power Supplies:Schematic Diagrams N/A A2PS1, A2PS2±15V/+5V Power Supply Outputs ±15Vdc @ 400mA maximum+5Vdc @ 2A maximum+28V Power Supply Output +28Vdc @ 9A maximumTwo DC power supplies are used in the Exciter/Upconverter drawer to provide power to themodules. A +28V supply is used to power the 2 Watt UHF Amplifier (A2) and the 20 Watt UHFAmplifier (A3) while all other modules are powered by a ±15V/+5V supply. The ±15V/+5V unit isa fully regulated, multiple output, linear power supply. The +28V supply is a high efficiency, singleoutput, switching power supply.2.3 Power Splitter:Schematic Diagram N/A CP1Insertion Loss (INPUT-OUTPUT) 6.25dBFrequency 450-810MHzThe Power Splitter is a low-loss Wilkinson design which divides the output signal from the Exciterdrawer into four signals of equal magnitude and phase. These four in-phase signals are used toseparately drive the four parallel amplifier modules (A3A1, A3A2, A4A1, A4A2) contained in theDual 300W UHF Power Amplifier drawers.2.4 Dual 300W Power Amplifier Drawer:Interconnection Diagram 40386003/Rev 56 A3, A4VISUAL RF IN (J1, J4) +36.7dBm peak visualVISUAL RF OUT (J2, J5) +55.0dBm peak visualVisual Gain (J1-J2, J4-J5) 16dB min.For final amplification this translator is composed of two Dual 300W Power Amplifier drawers (A3,A4) containing two 300W amplifier assemblies in each drawer. Each amplifier assembly amplifiesan equal portion of the divided signal from the Power Splitter and provides approximately 300 wattsof peak visual power. The individual 300W amplifier unit includes a 60W UHF Amplifier pallet(A1), a two-way Splitter (CP1), two 200W UHF Amplifier pallets (A2, A3), and a two-way Combiner(CP2). The Diagnostic/Control circuitry consists of a Current Monitor board (A1PC1) and a 150 Fthermostat (A1S1). Power is supplied to each 300W amplifier assembly by a Single Output +28V,750W Power Supply (PS1, PS2). Each drawer contains a Status Display board (PC1), whichdrives the LED indicators on the drawer’s front panel showing power supply and temperature status.
2232.4a 300W UHF Amplifier:Schematic Diagram 40386003/Rev 56 A3A1, A3A2, A4A1, A4A2Gain (J1-J2, J4-J5) 16dB min.Flatness (J1-J2, J4-J5) ±1dB from 470-860MHzEach 300W UHF Amplifier consists of a 60W UHF Amplifier (A1), a Splitter (CP1), two 200W UHFAmplifiers (A2, A3), a Combiner (CP2), a Circulator (HY1), a Current Monitor (PC1), and a 150 Fthermostat (S1). The 60W UHF Amplifier and the two 200W UHF Amplifiers are class AB,microstrip designs that provide at least 8dB and 7.5dB of gain, respectively. Each amplifier's gainvariation from 470 to 860MHz is typically ±0.75dB. The Splitter and Combiner are both two-sectionWilkinson couplers which separately contribute about 0.1dB of insertion loss. The Splitter dividesthe signal from the 60W UHF Amplifier into two signals of equal amplitude and phase. These twoin-phase signals are used to separately drive the two 200W UHF Amplifiers. The Combiner joinsthe amplified signals to form the output of the drawer. The Current Monitor is a Hall Effect sensorwhich monitors the current drawn by the 60W UHF Amplifier and the two 200W UHF Amplifiers,while applying a signal to the CURRENT SENSE line at pin 6 of connector J3. The information onthis line is processed by the fault monitoring/display section of the Control Board (PC1) locatedbehind the Front Panel (A5), which is mounted in the top rack position of the translator cabinet.The thermostat monitors the temperature of the 300W UHF Amplifier's heat sink by groundingpin B of A1PC1J2. If the temperature rises above 175 F, the thermostat opens, placing +5V onpin 10 of CONTROL plug J3 or J6. In turn, the Control Board (A5PC1) responds by placing 5V onPin 9 of CONTROL plug J3 or J6 disabling the corresponding 28V power supply (PS1 or PS2). Asa result, +28Vdc is removed from the 60W UHF Amplifier and the two 200W UHF Amplifiers whilethe appropriate TEMPERATURE indicator of the Status Display (PC1DS4 or PC1DS8) illuminatesyellow. At the same time the COLLECTOR BIAS indicator for that amplifier will extinguish.2.4b Status Display:Schematic Diagram 30386105/Rev 52 A3PC1, A4PC1On each Dual Power Amplifier drawer the Status Display board monitors the +28Vdc voltages fromthe corresponding Power Supply (PS1/PS2) as well as the status of each thermostat (A1S1/A2S1).The results are displayed on the COLLECTOR BIAS (DS1/DS5) and TEMPERATURE (DS4/DS8)indicators. When the translator's interlock circuit and the thermostats are closed, each powersupply provides +28Vdc to the corresponding 300W UHF Amplifier assemblies while thecorresponding DS1 and DS5 indicators are illuminated green and DS4 and DS8 are extinguished.When the interlock circuit is opened, each Power Supply is disabled, +28Vdc is removed from each300W UHF Amplifier, and the corresponding DS1 and DS5 indicators are extinguished while DS4and DS8 remain out. However, if the circuit breaker on the Front Panel (A5) is in the ON positionand the circuit breaker on the Front Panel of the Exciter drawer (A2) is in the OFF position,COLLECTOR BIAS indicators DS1 and DS5 will illuminate green. If either thermostat opens dueto high ambient temperature or an amplifier problem, each Power Supply is again disabled. Thisis indicated by the corresponding DS1 or DS5 indicators being extinguished, and TEMPERATUREindicators DS4 or DS8 illuminating yellow as appropriate.
2242.4c +28V Power Supply:Schematic Diagram N/A A3PS1, A3PS2, A4PS1, A4PS2The+28V Power Supply provides +28Vdc at up to 750W or 27A for the three amplifiers when thetranslator's interlock circuit is closed. The power supplies are high efficiency, switching types withpower factor correction and remote inhibit lines. These power supplies provide the supply voltageto the 60W and 200W UHF amplifier pallets within each 300W UHF Amplifier assembly. Thesupplies are energized from the Front Panel Control Board (A5PC1) which provides a +5Vdcenable signal to J1-2 of each supply via CONTROL plugs J3-9 and J6-9 of the amplifier drawers.This occurs only when the translator’s interlock circuits are closed.2.5 Power Combiner:Schematic Diagram N/A CP2Insertion Loss (INPUT-OUTPUT) 0.25dBFrequency 450-810MHzThe 4-way Power Combiner is a Wilkinson design that combines the four 300 watt amplified signalsfrom each of the Dual 300W UHF Power Amplifier Drawers (A3, A4). The recombined signal isthen applied to the Output Bandpass Filter (FL1) and Metering Coupler (DC1).2.6 Metering Coupler:Schematic Diagram N/A DC1Insertion Loss (J1-J2) <0.5dBFWD Coupling (J1-J3) 45dBREFLD Coupling (J2-J4) 45dBThe Metering Coupler is a four-port directional coupler that provides samples of the translator’sforward and reflected output power. These samples are used by the Metering Detector (A7) todrive the output % POWER meter.2.7 Front Panel:Interconnection Diagram N/A A5Located in the top rack position, the Front Panel holds the AC POWER circuit breaker, theMetering Detector (A7) and the Control Board (PC1).
2252.7a Metering Detector:Schematic Diagram 30368024/Rev P A5A7The Metering Detector contains separate but similar circuitry for monitoring the peak forward andaverage reflected power at the output of the translator. Samples of these two RF signals aresupplied by the Directional Coupler mentioned above.The front end or detector portion of each circuit is basically the same. Diodes CR2 and CR4,together with their surrounding components, convert the sampled on-channel RF signals to positivedc voltages proportional to the detected RF power. Detection of the sampled output carrier isaccomplished by CR2 in conjunction with R4 and C2 which form a time constant of 1 second. R4is the dc load while C1 and C11 form the RF ground of the visual power detector. Detection of thesampled reflected signal is the same except for a faster time constant furnished by R22/C6(1 millisecond). The positive dc voltages from the visual and reflected power detectors areprocessed by buffer amplifiers U1 and U2 which provide voltage gains of 1V/V and 2V/V,respectively. These buffer amplifiers also provide isolation between the % POWER meter and thedetector. The settings of potentiometers R9 and R27 determine the voltage level applied to the% POWER meter when the meter switch (PC1S1) is in its VISUAL or REFL positions, respectively.The aural power detector is not used in this application.A dc voltage proportional to the translator's forward output power is applied to pin 5 of connectorJ4, designated VIS PWR REF. This voltage is fed back to the Exciter drawer's Control Board(A2PC1). When the OUTPUT AGC switch (A2S2) is in its ON position, this voltage ultimatelycontrols the attenuation of the visual IF signal so that the translator's forward output power isautomatically maintained at its rated value.A dc voltage proportional to the translator's reflected output power is fed to pin 10 of comparatorU2. This voltage is compared to a reference voltage at pin 9 whose magnitude is determined bypotentiometer R30. With R30 properly set (see paragraph 3.5b), the voltage on pin 10 will begreater than the reference voltage whenever the translator's reflected power is more than 10% ofits rated forward power. As a result, the output of the comparator saturates in the positive modeapplying approximately +4Vdc to the VSWR OVLD line. This voltage instructs the Control Board(PC1) that a VSWR overload condition has been detected. If the translator's reflected power is lessthan 10% of its rated forward power, the voltage on pin 10 of comparator U2 will be less than thereference voltage. As a result, the comparator saturates in the negative mode, diode CR1 isforward biased, and approximately 0.7Vdc is applied to pin 7 of connector J4. This voltageinstructs the Control Board that no VSWR overload condition exists and, therefore, no action istaken.2.7b Control Board:Schematic Diagram 40386012/Rev 55 A5PC1The Control Board provides various monitoring, control and display functions in conjunction withan interface for remote monitoring. The circuitry of this board can be divided into four sections:(1) VSWR OVLD Monitoring/Interlock Control(2) 300 Watt UHF Power Amplifier Fault Monitoring/Display(3) 300 Watt UHF Power Amplifier Temperature Monitoring/DC Control(4) Metering Display
226The VSWR OVLD Monitoring/Interlock Control section is made up of two separate circuits. Onemonitors the VSWR OVLD and the Remote ON/OFF. This circuit is centered around two one-shotmultivibrator circuits, U1A and U1B, and a two-bit binary counter formed by flip-flops U2A and U2B.The other circuit is comprised of three OR gates U16A, C, D, and monitors the Fault lines for thefour 300 Watt Power Amplifiers.Under normal operating conditions the VSWR OVLD line (J2-14) is low and Q1 is turned off with+5V at its collector. The OUTput of U1A (pin 5) is low and becomes inverted by U10D before beingANDed with the REMOTE ON/OFF (J2-1) signal at U4A. The high output of U4A is inverted byU10E, placing a low at J1-1 which is fed to the Control Board of the Exciter (A2PC1). TheREMOTE ON/OFF line is high for an ON condition and low for an OFF condition. If the REMOTEON/OFF is not connected, R12 holds the line high simulating a REMOTE ON. U4D ANDs togetherthe normally low Q outputs (pins 5 and 9) of U2A and U2B producing a low at its output. When theExciter drawer’s POWER circuit breaker is set to ON, the outputs of U2A and U2B are cleared asQ2 provides a ground to the CLR pins 1 and 13. Q2 is turned on because the +15V supply risesto +5Vdc before the +5V supply does producing a negative voltage at the output of U7A. After the+5V supply reaches +5Vdc, +0.3V higher than the inverting input is clamped by zener diode VR1,the output of U7A goes high turning off Q2. The low output of U4D is ANDed with the normally lowOUTput of U1B at U4C which delivers a low to the Exciter drawer on pin J1-19, EXCITER VSWROVLD.When REFLected power exceeds 10% of the FWD power (or whatever ratio the trip point was setat), the VSWR OVLD line (J2-14) from the Metering Detector is pulled high. This action turns onQ1 grounding the TRIG inputs of U1A and U1B and the CLR input of U2A. The OUTput of U1Agoes high for 10 seconds, placing a high on J1-1 and shutting down the translator. For4 1/2 minutes the OUTput of U1B will also be high. When the translator is shut down, there is nooutput power and the VSWR OVLD line goes low turning off Q1. The resulting low to hightransition at the collector of Q1 triggers the clock input of U2A, flip-flopping its outputs so that Qis now high. If the reflected power exceeds 10% a second time within four minutes of the first, U1Awill again shut the translator down for 10 seconds and then bring it back up. U1B will continue tobe high and the Q outputs of U2A and U2B will count up one. A third occurrence of a VSWRoverload within approximately four minutes of the first will have the same results as the previousoccurrence except that, when U1A brings the system back on line, the flip-flop counter will reachbinary three; the Q outputs of U2A and U2B will both be high. This causes the output of U4D togo high which, together with the high OUTput of U1B, drives U4C high placing 5V on J1-19, theEXCITER VSWR OVLD line.The AMPL FAULT lines from the four 300 Watt UHF Power Amplifiers are monitored by OR gatesU16A and U16C. These lines are normally high, driving the output of U16D high and holding theRF DRIVE CONTROL line at +5V which connects back to the interlock section of the Exciter’sControl Board (A2PC1). Provided the power amplifier’s +28V Power Supply is turned on andoperating correctly, this line will stay high. Otherwise, it will go low and the Interlock circuit willopen placing the translator in standby.The 300 Watt UHF Power Amplifier Fault Monitoring/Display section gets its input signals from thefour CURRENT SENSE lines (J1-21, J1-3, J1-2, and J1-22) furnished by the Hall Effect CURRENTMONITORS (A1PC1 and A2PC2) mounted with each amplifier. Each of these signals is passedthrough its own unity gain amplifier (U20A through U20D) and is sent out on the REMOTECURRENT SENSE lines to an optional REMOTE MONITOR via J1-5, J1-6, J1-23 and J1-24.The four U6 op-amps, in conjunction with U7C, produce a voltage that is the average of the fourCURRENT SENSE voltages. With the four U6 op-amps wired as unity gain amplifiers, the voltageat pin 10 of U7C is equal to one half of the average input to U6A, U6B, U6C and U6D. Normallythe voltage at pin 8 of U7C is near 0V and negligible. The U8 op-amps compare each of the
227buffered CURRENT SENSE input signals to 86% of the average. When the translator is ON andthe 300 Watt UHF Power Amplifiers are operating normally, the outputs of U6A, U6B, U6C, andU6D are each greater than 86% of their average causing U8A, U8B, U8C, and U8D to saturate to+15V. The resistive voltage divider at the output of each U8 op-amp divides the +15V down to4.2V, a TTL level, for input to the inverters and buffers – U9 and U10. This causes the associatedU9 buffers to be high, illuminating the green section of indicators AMPL 1 (DS1), AMPL 2 (DS2),AMPL 3 (DS3), and AMPL 4 (DS4). At the same time the U10 inverters are low, forward biasingdiodes CR9, 11, 13 and 15 while extinguishing the red section of the indicators.If a CURRENT SENSE voltage from one of the 300W Amplifiers drops by more than 14%, theoutput of its corresponding U8 comparator will go to 15V and the inputs of the associated inverterand buffer will go to 0.5V. This extinguishes the green section of the associated AMPL indicatorand illuminates the red section.Because the four 300W Power Amplifiers (A3A1, A3A2, A4A1, A4A2) may not all draw the samecurrent, the CURRENT SENSE circuit sometimes can indicate that a fault has occurred when theamplifiers are actually operating within tolerance. To prevent this, each input has a balancepotentiometer, R20, R25, R29 and R34. These can be adjusted so that the inputs to each of thefour U6 op-amps are the same level. Section 3.7 explains the procedure for adjusting thesepotentiometers.The 300 Watt UHF Power Amplifier Temperature Monitoring/DC Control section takes theTHERMAL MONITOR lines from the Power Amplifiers as its inputs. Normally these lines (J1-15,J1-34, J1-16, and J1-35) are low. The circuit containing U7D and Q3 is identical to the U7A/Q2circuit in the VSWR OVLD section. When the translator is turned on, Q3 conducts clearingflip-flops U12A, U12B, U11A, and U11B. This sets the flip-flop outputs to their normal states whereQ is low and Q is high. The Q outputs drive the THERMAL OVLD INDICATOR lines along with theU19 buffers which drive the REMOTE THERMAL OVLD INDICATOR lines connector to REMOTEMONITOR plug J4 (pins 14 thru 17). Each Q output connects to a U14 NAND gate and, beingnormally low, the output of each NAND gate holds its connected transistor (Q4 through Q7) in theon condition so that the DC CONTROL lines are high.If the translator’s Interlock system opens, the FINAL PS INHIBIT at pin J1-29 will go low, drivingU14A, B, C, and D high. This will turn off their respective transistors (Q4 thru Q7) therebygrounding the DC CONTROL lines and shutting off each 300 Watt UHF Power Amplifier +28VPower Supply. With the +28V Power Supply off in each Power Amplifier, the voltage on theCURRENT SENSE lines will be 0V. This could cause one or more of the AMPLIFIER STATUSindicators to illuminate red incorrectly indicating a fault in an amplifier. Inverter U10C corrects this.A low on the FINAL PS INHIBIT line drives U10C high placing a small positive voltage on pin 9 ofU7C. This voltage is approximately 0.1V and is sufficient to keep the outputs of the U8 op-ampssaturated at +15V and the AMPLIFIER STATUS indicator illuminated green. The FINAL PSINHIBIT line is normally high and originates on the Exciter’s Control Board (A2PC1).When an amplifier’s heat sink temperature exceeds 150 C, its THERMAL MONITOR line goeshigh triggering the associated flip-flop and driving the corresponding THERMAL OVLD INDICATORline high. The REMOTE THERMAL OVLD INDICATOR line is also forced high along with NANDgate U14, which shuts down the PNP transistor supplying +5V to the amplifier’s DC CONTROL line.0V on one of the DC CONTROL lines shuts off the appropriate +28V Power Supply and itsassociated Power Amplifier. The affected amplifier and power supply will remain off until theMOMENTARY TEMP RESET switch is depressed triggering the CLR inputs on the U11 and U12flip-flops. (Removing and reapplying AC POWER to the translator will also clear the flip-flops.)Because this type of fault places an amplifier’s power supply in standby, its CURRENT SENSElevel drops to 0V causing the appropriate AMPL fault indicator to illuminate red.
228The RF ENABLE IN line at J2-8 takes the switched +28V from the EXCITER drawer (A2) andvoltage divides it to a high TTL logic level for the RF ENABLE OUT pin at J2-7. This provides alogic signal to the REMOTE MONITOR plug J4 (pin 23) indicating that RF drive has been enabled(high) or disabled (low).The Metering Display section consists of three 10-segment LED bar graphs (DS6, DS7 and DS8)and their drivers (U13, J17 and U18). Switch S1 selects the FORWARD or REFLected voltagedirectly from the Metering Detector at J1-36 or J1-17 and delivers it to the LED drivers. Unity gainop-amps U21C and U21A provide FORWARD METER and REFLected METER signals to theREMOTE MONITOR plug (J4) via pins J1-37 and J1-18 respectively.2.8 Output Filter:Schematic Diagram N/A FL1Insertion Loss (J1-J2) <0.5dBThe Output Filter, located in the bottom of the translator cabinet, is a multisection bandpassresonant cavity type. This filter is tuned to channel by the EMCEE test department and is not fieldserviceable. If it becomes necessary to have the filter retuned, contact the EMCEE CustomerService Department for a return authorization.
UHF SYNTHESIZER PROGRAMMING CHART (NTSC)Table 2 1Page 1 of 3Channel Visual Frequency(MHz) LO Freq(MHz) S4 S3 S2 S114 471.25 517 0 A 1 915 477.25 523 0 A 3 716 483.25 529 0 A 5 517 489.25 535 0 A 7 318 495.25 541 0 A 9 119 501.25 547 0 A A F20 507.25 553 0 A C D21 513.25 559 0 A E B22 519.25 565 0 B 0 923 525.25 571 0 B 2 724 531.25 577 0 B 4 525 537.25 583 0 B 6 326 543.25 589 0 B 8 127 549.25 595 0 B 9 F28 555.25 601 0 B B D29 561.25 607 0 B D B30 567.25 613 0 B F 931 573.25 619 0 C 1 732 579.25 625 0 C 3 533 585.25 631 0 C 5 334 591.25 637 0 C 7 135 597.25 643 0 C 8 F36 603.25 649 0 C A D
UHF SYNTHESIZER PROGRAMMING CHART (NTSC)Channel Visual Frequency(MHz) LO Freq(MHz) S4 S3 S2 S1Table 2 1Page 2 of 337 609.25 655 0 C C B38 615.25 661 0 C E 939 621.25 667 0 D 0 740 627.25 673 0 D 2 541 633.25 679 0 D 4 342 639.25 685 0 D 6 143 645.25 691 0 D 7 F44 651.25 697 0 D 9 D45 657.25 703 0 D B B46 663.25 709 0 D D 947 669.25 715 0 D F 748 675.25 721 0 E 1 549 681.25 727 0 E 3 350 687.25 733 0 E 5 151 693.25 739 0 E 6 F52 699.25 745 0 E 8 D53 705.25 751 0 E A B54 711.25 757 0 E C 955 717.25 763 0 E E 756 723.25 769 0 F 0 557 729.25 775 0 F 2 358 735.25 781 0 F 4 159 741.25 787 0 F 5 F
UHF SYNTHESIZER PROGRAMMING CHART (NTSC)Channel Visual Frequency(MHz) LO Freq(MHz) S4 S3 S2 S1Table 2 1Page 3 of 360 747.25 793 0 F 7 D61 753.25 799 0 F 9 B62 759.25 805 0 F B 963 765.25 811 0 F D 764 771.25 817 0 F F 565 777.25 823 1 0 1 366 783.25 829 1 0 3 167 789.25 835 1 0 4 F68 795.25 841 1 0 6 D69 801.25 847 1 0 8 B
UHF SYNTHESIZER PROGRAMMING CHART (PAL)For PAL operation the grounds to Pins 21 and 23 of U1 (MC145152) must be removed.Table 2 1Page 1 of 2Channel Visual Frequency(MHz) LO Freq(MHz) S4 S3 S2 S121 471.25 510.15 0 9 F 622 479.25 518.15 0 A 1 E23 487.25 526.15 0 A 4 624 495.25 534.15 0 A 6 E25 503.25 542.15 0 A 9 626 511.25 550.15 0 A B E27 519.25 558.15 0 A E 628 527.25 566.15 0 B 0 E29 535.25 574.15 0 B 3 630 543.25 582.15 0 B 5 E31 551.25 590.15 0 B 8 632 559.25 598.15 0 B A E33 567.25 606.15 0 B D 634 575.25 614.15 0 B F E35 583.25 622.15 0 C 2 636 591.25 630.15 0 C 4 E37 599.25 638.15 0 C 7 638 607.25 646.15 0 C 9 E39 615.25 654.15 0 C C 640 623.25 662.15 0 C E E41 631.25 670.15 0 D 1 642 639.25 678.15 0 D 3 E43 647.25 686.15 0 D 6 644 655.25 694.15 0 D 8 E
UHF SYNTHESIZER PROGRAMMING CHART (PAL)Channel Visual Frequency(MHz) LO Freq(MHz) S4 S3 S2 S1For PAL operation the grounds to Pins 21 and 23 of U1 (MC145152) must be removed.Table 2 1Page 2 of 245 663.25 702.15 0 D B 646 671.25 710.15 0 D D E47 679.25 718.15 0 E 0 648 687.25 726.15 0 E 2 E49 695.25 734.15 0 E 5 650 703.25 742.15 0 E 7 E51 711.25 750.15 0 E A 652 719.25 758.15 0 E C E53 727.25 766.15 0 E F 654 735.25 774.15 0 F 1 E55 743.25 782.15 0 F 4 656 751.25 790.15 0 F 6 E57 759.25 798.15 0 F 9 658 767.25 806.15 0 F B E59 775.25 814.15 0 F E 660 783.25 822.15 1 0 0 E61 791.25 830.15 1 0 3 662 799.25 838.15 1 0 5 E63 807.25 846.15 1 0 8 664 815.25 854.15 1 0 A E65 823.25 862.15 1 0 D 666 831.25 870.15 1 0 F E67 839.25 878.15 1 1 2 668 847.25 886.15 1 1 4 E
iiiSECTION IIIMAINTENANCE3.1 Periodic Maintenance Schedule ......................................... 3 13.2 Recommended Test Equipment .......................................... 3 13.3 Troubleshooting ........................................................ 3 23.3a Front Panel Control Board Indicators .................................... 3 23.3b Dual 300W Power (Final) Amplifier Drawer Indicators ....................... 3 23.3c UHF Exciter/Upconverter Indicators ..................................... 3 33.3d Receiver Drawer Indicators ........................................... 3 33.3e TU1000F V/U Troubleshooting Chart .................................... 3 43.4 Translator Alignment ................................................... 3 73.4a Receiver Alignment ................................................. 3 73.4b Exciter/Upconverter Alignment........................................ 3 113.5 Output Power Calibration .............................................. 3 123.5a Forward Power .................................................... 3 123.5b Reflected Power (Optional) ........................................... 3 133.6 Precorrection Adjustment .............................................. 3 143.7 Control Board Setup ................................................... 3 143.8 Remote Monitor Signal Levels .......................................... 3 163.9 Spare Modules and Components ........................................S 1
3 1SECTION IIIMAINTENANCE3.1 Periodic Maintenance Schedule:CHECK RECOMMENDATIONALIGNMENT Upon installation and at one-year intervalsthereafter (see section 3.4).OUTPUT POWER CALIBRATION SAME AS ABOVE (see section 3.5).FANS Inspect as often as possible (at least monthly)and clean when necessary. No lubricationneeded.3.2 Recommended Test Equipment:EQUIPMENT MANUFACTURER MODEL #Digital Multimeter HEWLETT PACKARD E2378AOscilloscope TEKTRONIX 2232Sweep Generator WAVETEK 200150 Ohm RF Detector TELONIC BERKELEY 855320dB Attenuator NARDA 766-2020dB Directional Coupler NARDA 3001-2050 Ohm, 1000W Dummy Load BIRD 8833Power Meter HEWLETT PACKARD 435BStep Attenuator KAY 1/432Frequency Counter HEWLETT PACKARD 5386ASpectrum Analyzer HEWLETT PACKARD 8594ENTSC Video Generator TEKTRONIX TSG100
3 23.3 Troubleshooting:If the output signals from the translator appear distorted, noisy or nonexistent, consider thefollowing procedure as a troubleshooting aid. This procedure assumes the translator wiring as wellas the cabling and connectors are trouble free. It also assumes the Receiver drawer is receivingthe appropriate input signal while providing the required visual and aural IF carriers. The generalproblem area will be indicated by simply checking the front panel diagnostic lights as well as the% POWER meters. The diagnostic indicators are located on the front panels of the UHF Exciter/Upconverter (A2), the Front Panel (A5) and the Dual 300W Power (Final) Amplifier drawers (A3,A4).3.3a Front Panel Control Board Indicators: 1. Under normal operation all indicators will be lit green and the RF POWER meter will furnisha 100% indication with the meter switch placed to FWD. 2. Under standby conditions, all indicators will be lit green. 3. Any AMPLIFIER STATUS/AMPL 1, 2, 3 or 4 indicator which turns red during normaloperation signifies an amplifier module or power supply malfunction within the drawerspecified. Typically the COLLECTOR BIAS LED associated with the failed amplifier orpower supply will extinguish unless the announced amplifier failure is an open. In eithercase, replace the malfunctioning Final Amplifier drawer. If the operator has the appropriatetechnical experience to locate the malfunction, he may repair the Final Amplifier drawer byreplacing its power supply or its power amplifier heat sink assembly instead of replacing theentire drawer.3.3b Dual 300W Power (Final) Amplifier Drawer Indicators:COLLECTOR BIAS indicator monitors the voltage applied to the 60 watt driver and two 200 wattfinal amplifier pallets within the 300W amplifier module. If the power supply malfunctions, thisgreen indicator will turn off. When a COLLECTOR BIAS indicator goes out, the associated FrontPanel Control Board (A5PC1) AMPLIFIER STATUS/AMPL 1, 2, 3 or 4 indicator will turn red.The TEMPerature indicator monitors the thermostat fixed to the heat sink of the drawer's amplifiersection. If the heat sink temperature exceeds 150 F due to high ambient temperature or becauseof an amplifier malfunction, the thermostat will open shutting off the amplifier's power supply andilluminating the yellow TEMP indicator. Since the 28Vdc power supply is now off, theCOLLECTOR BIAS LED will have turned off and the related Control Board AMPLIFIER STATUS(1, 2, 3 or 4) indicator will turn red. If any of the above malfunctions occur, the Final Amplifierdrawer should be substituted or, depending on the problem's location, the drawer's power supplyor amplifier section should be replaced.
3 33.3c UHF Exciter/Upconverter Indicators:Under normal operating conditions, the OPERATE/ALIGN and STBY/OPERATE switches will bein the OPERATE position, the FINAL BIAS, ON, OPERATE, SYNTH LOCK and DRIVER AMPindicators should be illuminated green and the VSWR OVLD and TEMP EXCITER LEDs shouldbe extinguished.If the DRIVER AMP LED is lit red, the 20 watt amplifier has failed. Replace the 20 watt amplifiermodule.The green SYNTH LOCK indicator turns off when the Exciter's frequency synthesizer is notproperly locked. Also, the green FINAL BIAS and ON LEDs will turn off. If the problem persists,the synthesizer should be replaced.An extinguished ON LED with all other LEDs remaining in their normal states indicates a fault inthe Exciter’s +28V power supply. Replace the power supply.The TEMP indicator monitors the thermostat fixed to the heat sink of the drawer's 20 WattAmplifier. If the heat sink temperature exceeds 150 F due to high ambient temperature orbecause of an amplifier malfunction, the thermostat will open, illuminating the Exciter’s yellowTEMP indicator. This will also cause the FINAL BIAS and ON LEDs to turn off indicating that the+28V has been removed from the Exciter’s 2 watt and 20 watt amplifiers. Replace any faultymodules and ensure that fans are operational and have adequate room to ventilate the drawer.If the FINAL BIAS and ON LEDs are extinguished for 10 seconds and then come back on with allother LEDs remaining in their normal states, the system was in a state of temporary VSWRoverload. If this occurs two more times within a 4 1/2 minute period, the VSWR OVLD indicatorwill illuminate and the translator will be placed in a permanent standby mode. This condition isaccompanied by the FINAL BIAS and ON indicators remaining off, indicating that the +28V hasbeen removed from the Exciter’s 2 watt and 20 watt amplifiers. Under this condition, the cause ofthe VSWR problem at the translator's output must be cleared before lifting the VSWR OVLDRESET switch to reactivate the unit. If the FINAL BIAS and ON LEDs are extinguished and do notcome back on and all other LEDs remain in their normal states, this indicates that the appropriatereceive signal is not being detected at the input of the Receiver drawer. Check the receiveantenna, preamplifier (if used) and the down lead cabling to ensure that the receive signal ispresent. If the receive signal is present, troubleshoot the Receiver.The OPERATE indicator will be green if the position of the OPERATE/ALIGN switch is up. Thisis the appropriate position when the translator is on the air. The OPERATE/ALIGN switch shouldonly be in the ALIGN position (down) while performing sweep alignment of the Exciter. This switchposition sets the AGC for minimum signal attenuation.3.3d Receiver Drawer Indicators:The CARRIER PRESENT green LED indicates that the Receiver is seeing an input signal ofappropriate frequency and amplitude necessary to develop the IF AGC voltage which places thetranslator in operation.
3 43.3e TU1000F V/U Troubleshooting Chart:The following chart is meant as an aid for uncovering faults that have developed in this translator.During normal operation, all indicator LEDs are green, except the VSWR OVLD LED which isnormally extinguished. This chart lists the LEDs that are indicating a fault (i.e., are not in theirnormal state). If a problem develops, note the state of the indicator LED and compare it to thechart.TU1000F V/U TROUBLESHOOTING CHARTPROBLEM INDICATORS CAUSE SOLUTIONNO OUTPUTPOWER ALL EXCITERINDICATORS UNLIT +5VDC Power Supplyfaulty or shorted Check Meter reading for5V. Replace powersupply if necessary.SYNTH LOCK UNLITON UNLITFINAL BIAS UNLITDefective Synthesizer Check synthesizer forcorrect output level andfrequency. Replace iffaulty.FINAL BIAS UNLITON UNLIT Operate/Standby switchon Standby Place switch to Operate.Turned off by Remote Ensure translator has notbeen turned off byremote.No signal detected atinput of Receiver Check cabling. Trouble-shoot Receiver if faulty.Temporary VSWRoverload Will return after10 seconds.ON UNLIT +28V Exciter Supplyfaulty Replace power supply.DRIVER AMP RED 20 Watt Amplifier faulty Replace module.TEMP YELLOWFINAL BIAS UNLITON UNLITHigh ambienttemperature Ensure fans are opera-tional and have adequateroom ventilation. Ifproblem persists, checkfor faulty operation ofamplifier and replace ifnecessary.
TU1000F V/U TROUBLESHOOTING CHARTPROBLEM INDICATORS CAUSE SOLUTION3 5NO OUTPUTPOWER VSWR OVLD REDON UNLITFINAL BIAS UNLITVSWR overload hasoccurred. Check the transmissionline and antenna for highVSWR. Repair orreplace any componentwith a high VSWR.Clear problem attranslator’s output, thenlift the VSWR OVLDRESET switch.No fault indicated Receiver failure Repair Receiver.Bad cable Check cabling betweenthe Receiver and Exciter.LOW OUTPUTPOWER ORDISTORTEDOUTPUTNo Fault indicated Output Power Calibrationis incorrect See Section 3.5.Receiver malfunction Repair Receiver.High loss in one of themodules Test each module forcorrect gain/loss. SeeSignal Flow Diagram(Fig. 3 2) for gains/losses.RF chain misaligned See Section 3.4.Precorrector improperlyadjusted or not turned on See Section 3.6.TEMPERATURE YELLOWCOLLECTOR BIAS UNLITAMPL 1,2,3 or 4 UNLITHeat sink temperature toohigh due to high ambienttemperatureEnsure fans are opera-tional and have adequateroom ventilation.Heat sink temperature toohigh due to amplifier mal-functionReplace faulty amplifierassembly.COLLECTOR BIAS UNLITAMPL 1,2,3 or 4 RED Faulty +28V PowerSupply Replace power supply.Power supply exceededcurrent limit due to mal-functioning amplifiermoduleReplace amplifierassembly.
TU1000F V/U TROUBLESHOOTING CHARTPROBLEM INDICATORS CAUSE SOLUTION3 6LOW OUTPUTPOWER ORDISTORTEDOUTPUTAMPL 1,2,3 or 4 RED Faulty 300W Amplifier Replace amplifierassembly.CONTACTORCYCLES 28VDC reading on Exciter% power meter will cycle Internal Short on 28V Unplug each module andcheck for a short. Replace module(s) oramplifier assembly asneeded.Power Supply folds backwhen under a load Replace Power Supply.HIGH OUTPUTPOWER ANDDISTORTEDSeveral red bars on % RFPOWER meter lit andPOWER ADJUST does notreduce outputAGC loop is broken Ensure OPERATE/ALIGNset to OPERATE.Misaligned AGC trap in IFAGC Amplifier Readjust visual IF trapinductor core.IF AGC Amplifier orLimiter/Output AGCcircuit failureReplace IF AGC Amplifieror Limiter/Output AGCPC board.Failure in Exciter IFConverter Replace IF Convertermodule.
3 73.4 Translator Alignment:3.4a Receiver Alignment: 1. Remove the four screws on the front panel of the Receiver drawer, carefully pull out thedrawer, and remove the top cover. Set up the test equipment as shown in Figure 3 4.Place the Receiver's front panel AC POWER switch (S2) to ON and place the Exciter’s frontpanel AC POWER switch (A2CB1) to OFF. 2. Disconnect the coaxial cable from the output connector of the Vectron Oscillator. Connecta power meter to the output of the oscillator (point A of Figure 3 4). An indication of 3mWto 6mW should be present. (If the oscillator’s output power is low or nonexistent, return theoscillator to EMCEE for repair or replacement as this is not a field repairable item.) 3. Connect a frequency counter to the oscillator output and wait approximately fifteen (15)minutes for the oscillator to heat or until the frequency stabilizes. 4. If the measured frequency differs by more than 50Hz from the oscillator’s designatedfrequency, proceed to step #5. If the measured frequency is within 50Hz of the designatedfrequency, then remove the frequency counter from the output of the oscillator, reconnectthis module to the input of the multiplier and proceed to step #7. 5. Remove the cover screw from the side of the oscillator exposing the access hole and, witha small tuning tool, slowly vary the frequency adjust potentiometer for the correct frequency. 6. Remove the frequency counter from the output of the oscillator and reconnect this moduleto the input of the multiplier (A3). 7. Remove the retaining screws and lift the multiplier module off the Receiver's chassis.Connect a spectrum analyzer to the output connector (J2) of the multiplier (point B ofFigure 3 4). Tune the spectrum analyzer to either the second, fourth, or sixteenth harmonicof the oscillator frequency depending on whether a X2, X4, or X16 Multiplier is being used.(The X2 Multiplier is used for VHF channels 2-6, the X4 Multiplier is used for VHFchannels 7-13, and the X16 Multiplier is used for UHF channels 14-69). Carefully "touch up"the capacitors accessible through the bottom cover of the module for maximum power(10 to 30mW) at the proper harmonic of the oscillator frequency. If power is low ornonexistent, proceed to step #8, #9, or #10 depending on whether a X2, X4, or X16Multiplier is being used. Otherwise, proceed to step #11. 8. X2 Multiplier (Ch.2-6)a. Remove the module's bottom cover and tune capacitors C7, C12, C13, C14, C15,C16, C17 and inductors L6, L7, L8 for a minimum of 10mW at the oscillator's secondharmonic (see Schematic B280-35). Insure that the fundamental and other harmonicsare at least 20dB below the second harmonic.NOTE: If the X2 Multiplier's output power is low or nonexistent, troubleshoot thecircuit and repeat the tuning procedure given in step #8a.
3 8b. Replace the bottom cover and slightly readjust capacitors C12, C13, C14, C15, C16,and C17 for the specifications stated in step #8a. When these specifications areobtained, proceed to step #11. 9. X4 Multiplier (Ch.7-13)a. Remove the bottom cover of the module and disconnect the jumper wire attached toterminal post D on the X4 Multiplier's PC board (see Schematic C331-24).b. Solder an open-ended 50 ohm coaxial cable to terminal posts D (center conductor)and K (shield) and connect a spectrum analyzer to the opposite end of the coaxialcable.c. Tune the spectrum analyzer to the second harmonic of the oscillator's outputfrequency and adjust capacitors C7, C12 through C17 and inductors L6, L7, and L8 formaximum power (25 to 55mW) at the second harmonic of the oscillator's outputfrequency. Insure that the other harmonics are at least 40dB below the secondharmonic by tuning capacitors C14 and C16 near minimum coupling (least capaci-tance) without sacrificing power.d. Remove the coaxial cable from terminal posts D and K. Resolder the jumper wirewhich connects terminal posts D and E.e. Disconnect the jumper wire attached to terminal post M on the X4 Multiplier's PCboard (see Schematic C331-24).f. Solder the open-ended 50 ohm coaxial cable to terminal posts M (center conductor)and N (shield). Connect a spectrum analyzer to the opposite end of the coaxial cable.g. Tune the spectrum analyzer to the frequency of the oscillator's fourth harmonic andadjust capacitors C19, C22, and C23 for maximum power (75 to 100mW) at thatfrequency. Insure that all other harmonics are at least 20dB lower.h. Remove the coaxial cable from terminal post M and ground. Resolder the jumper wireto terminal post M.i. Attach the spectrum analyzer to the output connector (J2) of the X4 Multiplier module(point B of Figure 3 4).j. Tune the spectrum analyzer to the frequency of the oscillator's fourth harmonic andadjust capacitors C19, C22, C23, C26, C27, and C29 for maximum power (10 to30mW) at the same frequency. Insure that all other harmonics are at least 20dB downfrom the fourth harmonic.NOTE: If the output power of any section of the X4 Multiplier is low or nonexistent,troubleshoot the circuit responsible and repeat the alignment procedure.k. Replace the bottom cover and slightly readjust capacitors C19, C22, C23, C26, C27,and C29 for the specifications stated in step #9j. When the specifications areobtained, proceed to step #11.
3 910. X16 Multiplier (Ch.14-69)a. For tuning this multiplier fabricate a test cable by soldering a .01 F capacitor to thecenter conductor of an open-ended 50 ohm cable. Ensure that there is enough outerconductor (braid) available for soldering at the open end and attach a good RFconnector (BNC, N, SMA) to the opposite end.b. Turn the multiplier module over and solder the open capacitor lead of the test cableto the output side of coupling capacitor C8 (see Schematic 30367226) and connect theopposite end of the cable to a spectrum analyzer. Make sure that the test cable outerconductor is soldered to the PC board’s ground plane.c. Adjust the spectrum analyzer to view the fourth harmonic of the oscillator and tunemultiplier capacitors C1, C2, C3, C4, C5 and C33 for maximum power at thatfrequency.d. Remove the cable from C8 and solder the capacitor lead to the output side of couplingcapacitor C17. Remember to solder the braid to ground.e. Adjust the analyzer to observe the eighth harmonic of the oscillator and tunecapacitors C9, C10 and C11for maximum amplitude at that frequency.f. Unsolder the test cable from C17 and ground and attach a cable to the multiplieroutput connector J2 (SMA) and connect the opposite end to the spectrum analyzer.g. Readjust the spectrum analyzer to observe the sixteenth harmonic of the oscillator andtune multiplier capacitors C21, C22, C23, C30, C31 and C32 for maximum power.h. Carefully retune all the multiplier capacitors for maximum power at the sixteenthharmonic. The multiplier should furnish 20 to 25mW of power.NOTE: If the output power of any section of the X16 Multiplier is low or nonexistent,troubleshoot the circuit responsible and repeat the tuning procedure.11. Reconnect the output of the Multiplier to the LO port (J3) of the Downconverter/Preamplifierand secure the module to the bottom of the Receiver drawer.RF Amplifier Chain12. Place the Receiver's front panel OPERATE/ALIGN switch (S1) to ALIGN and set up the testequipment as shown in Figure 3 5 with the 10dB attenuator connected to the output ofeither the VHF or UHF Bandpass Filter (point A of Figure 3 5).13. Adjust the sweep and marker generator for an oscilloscope display width of 15MHz at theinput frequency of the Receiver. To prevent overdriving any amplifiers, set the oscilloscopefor maximum sensitivity.14. a. For a VHF input: Adjust capacitors C1 through C5 of the VHF Bandpass Filter (FL1)to obtain a frequency response as that shown in Figure 3 6A. There should be lessthan 2dB of insertion loss.
310b. For a UHF input: Tune capacitors C1, C2, and C3 of the UHF Bandpass Filter (FL1)for a frequency response as that shown in Figure 3 6A with less than 3dB of insertionloss. Only if absolutely necessary, adjust the Variable Coupling Barriers and inductorsL1 and L4 for the correct response (see Schematic 10331209).15. Remove the attenuator from the output of either the VHF or UHF Bandpass Filter (FL1) andconnect the attenuator to the output of the Downconverter/Preamplifier module (point B ofFigure 3 5). Reconnect either the VHF or UHF Bandpass Filter to the input of theDownconverter/Preamplifier (A1).16. Check the output of the Downconverter/Preamplifier for a gain (with conversion) of 3dB anda frequency response as shown in Figure 3 6A. Correct any slight frequency responsevariations (tilt) with either the VHF or UHF Bandpass Filter as explained in step #14 of thissection. If there are any major frequency response or gain problems (>±1dB), sweep andtroubleshoot the Downconverter/Preamplifier by itself.17. Remove the attenuator from the output of the Downconverter/Preamplifier and connect theattenuator to the output of the IF Amplifier w/SAW Filter (point C of Figure 3 5). Reconnectthe output of the Downconverter/Preamplifier to the input of the IF Amplifier w/SAW Filter(A2).18. Check for a frequency response as shown in Figure 3 6B and a minimum gain of 20dB. Ifthere is a major discrepancy in frequency response or gain (±2dB), sweep and troubleshootthe IF Amplifier w/SAW Filter by itself.19. Disconnect the attenuator from the output of the IF Amplifier w/SAW Filter and connect theattenuator to the output of the Receiver drawer (point D of Figure 3 5). Reconnect theoutput of the IF Amplifier w/SAW Filter to the input of the IF AGC Amplifier (A3).20. With the Receiver's front panel OPERATE/ALIGN switch in the ALIGN position, adjust theIF AGC Amplifier's TILT ADJ control (R31) to obtain a flat frequency response as shown inFigure 3 6B. The TILT ADJ potentiometer is accessible through the top of the IF AGCAmplifier module. Check the IF AGC Amplifier for a gain of approximately 25dB. (This gainis dependent on the +5Vdc reference voltage provided to the IF AGC Amplifier's variablepin diode attenuator when the Receiver's OPERATE/ALIGN switch is in the ALIGN position.)Limiter/Output AGC Calibration:21. Connect an IF modulator to the input of the IF AGC Amplifier (point C of Figure 3 5).Adjust the modulator to deliver the visual carrier frequency (45.75MHz) at 39dBm peakpower. Place the Receiver's front panel OPERATE/ALIGN switch (S1) to OPERATE.22. Connect a power meter or spectrum analyzer to the output of the Receiver drawer (point Dof Figure 3 5).23. Adjust the AGC REF potentiometer (PC1R8) fully CW and adjust the LIMITER ADJpotentiometer (PC1R13) fully CCW. These two potentiometers are located on the Limiter/Output AGC board (see Schematic B331-34).24. Adjust the IF AGC Amplifier's GAIN ADJ potentiometer (A3R15) for a +2dBm signal at theoutput of the Receiver drawer (see Schematic C331-37). The GAIN ADJ control isaccessible through the top of the IF AGC Amplifier module.
31125. Recalibrate the modulator so that it now delivers a +1dBm peak visual signal at 45.75MHzto the IF AGC Amplifier module. Slowly adjust IF AGC Amplifier inductor L3 of the visualtank circuit so that a minimum power indication is seen on the external power meter orspectrum analyzer. Inductor L3 is accessible through the top of the IF AGC Amplifiermodule.26. Place the Receiver's front panel AGC ON/OFF switch to OFF. Adjust the AGC REFpotentiometer (PC1R8) for a 6dBm output level from the Receiver drawer.27. Slowly adjust the LIMITER ADJ potentiometer (PC1R13) CW until the 6dBm output levelbegins to fluctuate (i.e., as the limiter circuit begins to activate).28. Readjust the AGC REF potentiometer to bring the output level from 6dBm down to 9dBm.29. Short capacitor C2 on the Limiter/Output AGC board.NOTE: K1 on the Limiter/Output AGC board will deenergize causing the AGC voltageto be replaced by the PRE AGC REF voltage. This voltage is set by the PREAGC REF ADJ potentiometer (PC1R25).30. Adjust the PRE AGC REF ADJ potentiometer (PC1R25) for 8dBm at the output of theReceiver drawer. This potentiometer is located on the Limiter/Output AGC board.31. Remove the short from across C2.32. Monitor test point TP1 (OUTPUT AGC) on the Limiter/Output AGC board and vary theReceiver's front panel AGC ADJUST potentiometer (R3) for a 0Vdc reading at TP1.33. Place the Receiver's front panel AGC ON/OFF switch to ON.34. If necessary, adjust the Receiver's output power level for 6dBm using the front panel AGCADJUST potentiometer.35. Disconnect the power meter or spectrum analyzer from the output of the Receiver drawer.Reconnect the Receiver drawer's IF OUTput to the Exciter/Upconverter drawer's IF INput.Reconnect the IF AGC Amplifier's input to the output of the IF Amplifier w/SAW Filter.36. Reinstall the top cover to the translator's Receiver drawer. Carefully slide the drawer backinto the cabinet and secure it properly.3.4b Exciter/Upconverter Alignment: 1. If the Exciter is operating, place the Exciter’s OPERATE/STANDBY switch to STANDBYand the OPERATE/ALIGN switch to ALIGN. Remove the four screws on the front panel ofthe Exciter/Upconverter drawer, carefully pull out the drawer, and remove its top cover.Leave the Power Adjust control as it would be for normal operation. 2. Remove the Receiver cable attached to the IF INPUT connector, J1. Set up the testequipment as shown in Figure 3 7. Connect the VHF sweep generator's RF output to theIF INPUT connector of the Exciter. Set the VHF sweep generator to sweep from 36 to50MHz. (Use 45.75MHz and 41.25MHz markers if available.) Tune the spectrum analyzer
312to the UHF Synthesizer's LO frequency. The frequency corresponds to the translator'soutput channel as shown in Table 2 1. 3. Place the OPERATE/STANDBY switch to OPERATE. Adjust C1, C2, and C3 on the UHFBandpass Filter to obtain the frequency response shown in Figure 3 6A. 4. If the translator's output channel is being changed to one that is 40MHz or more from thefactory preset, connect a spectrum analyzer to the 30dB attenuator in Figure 3 7 to ensurethat the sweep appears on the low side of the LO. Tune the spectrum analyzer to the UHFSynthesizer’s LO frequency as shown in Table 2 1, UHF Synthesizer Programming Chart.Program the synthesizer for the new channel and look for the LO carrier on the analyzer.Tune the analyzer 45.75MHz (38.9MHz for PAL B/G) below the LO frequency and tune C1,C2 and C3 of the UHF Bandpass Filter for maximum amplitude of the sweep generatorsignal on the spectrum analyzer. Replace the analyzer with the sweeper diode detector andadjust the UHF Bandpass Filter for the response of Figure 3 6A as shown on theoscilloscope. 5. Remove the sweep generator cable from the Exciter drawer IF INput connector (J1) anddisconnect the RF detector from the drawer’s RF OUTput (J2). Replace the Exciter’s topcover and push the drawer into the rack replacing the four front panel screws. Reconnectthe Receiver cable to the IF INput connector (J1) and the Splitter’s RF cable to the IFOUTput connector (J2).3.5 Output Power Calibration:To ensure proper transmission, the output power level and % RF Power meter calibration shouldbe checked once every year. With the meter switch in the FWD position, the % RF Power meterhas been factory calibrated for 100% with the translator providing 1000 watts peak visual and50 watts average aural. The average power measurements in this calibration procedure assumethat the composite signal from the translator has the aural carrier 13dB down from the visual withthe visual carrier having 87.5% video modulation and 0% (sync only) average picture level (APL).Average power levels employing 50% APL (stairstep/ramp/flat field) are included in bracketsfollowing the power levels at 0% APL. It is also assumed that the setup in Figure 3 8 is being usedand the output of the receiver drawer has been currently calibrated. If the received broadcastchannel frequency is in the VHF band (Ch.2-13), the mixer may be removed and the VHF outputof the agile modulator can be connected directly to the RF INput (J1) of the Receiver drawer.3.5a Forward Power: 1. With the Exciter OPERATE/STANDBY switch on STANDBY, set up the test equipment asshown in Figure 3 8. 2. Verify that the modulator is providing 87.5% video modulation and the aural carrier is 13dBdown from the visual carrier. With the Receiver OPERATE/ALIGN switch in the OPERATEposition and the Meter Switch on FWD, place the Exciter OPERATE/STANDBY switch toOPERATE.
313 3. To set the output power, adjust the Exciter’s POWER ADJUST control for an external powermeter reading of 645W [430W]. Note that 1000W peak visual at 0% [50%] APL plus50 watts average aural for a 13:1 peak visual to average aural ratio equals 645W [430W]. 4. To check or adjust visual to aural ratio, replace the power meter in Figure 3 8 with aspectrum analyzer. Adjust the aural carrier level on the modulator for the desired ratio.Remove the spectrum analyzer and return the power meter to the setup to reset the outputpower. Set the POWER ADJUST again for an external power meter reading of 595W[380W] visual plus the average aural carrier level for the set ratio. Modulators are presetby EMCEE test department. 5. With the external power meter reading correctly, place the Front Panel (A5) meter switchto FWD and check the translator's % RF Power meter for a 100% indication. If this readingis not obtained, adjust potentiometer R9 of the Metering Detector located behind the FrontPanel (A5) and accessible through the METER ADJUST hole marked FWD.3.5b Reflected Power (Optional): 6. Through the METER ADJUST access hole marked VSWR OVLD, adjust potentiometer R30of the Metering Detector fully clockwise to disable the VSWR overload detection circuit.Place the % RF POWER meter switch to REFL. 7. Place the Exciter’s OPERATE/STANDBY switch to STANDBY and the OPERATE/ALIGNswitch to ALIGN. Disconnect and reverse the FWD (J3) and REFLD (J4) coupling portcables on the Metering Coupler (DC1). J3 (REFLD) of the Metering Detector (A5A7) shouldnow be connected to J3 (FWD) of the Metering Coupler (DC1). This simulates an opencircuit at the translator's RF OUTput (J2) delivering maximum returned power to thereflected power detector. Insert a 1dB step attenuator between the Receiver and theExciter’s IF INput connector and set the attenuator for 10dB of attenuation. 8. Place the OPERATE/STANDBY switch to OPERATE. Remove attenuation from the stepattenuator until an external power meter reading of 645W [430W] is reached. Check thefront panel % RF POWER meter for a 100% [70%] reading. If the meter is incorrect, adjustit using potentiometer R27 of the Metering Detector found behind the METER ADJUST holemarked REFL. 9. Decrease the translator's power to 10% using the step attenuator (an external power meterreading of 64.5W [43W]). This power level is used for setting the trip point of the VSWRoverload detection circuit. Adjust R30 of the Metering Detector, found through the METERADJUST access hole marked VSWR OVLD, slowly counterclockwise until the front panelVSWR OVLD indicator illuminates red and the translator’s output power drops to zero.10. Check the VSWR OVLD trip point by adding an additional 1dB of attenuation in the stepattenuator. Press the momentary VSWR RESET switch to reactivate the translator andremove an additional 1or 2dB of attenuation from the step attenuator. The VSWR OVLDcircuit should again trip. If it does not, repeat this section beginning at step #6.11. Place the Exciter’s OPERATE/STANDBY switch to STANDBY. Return the metering cablesto their original coupler ports. Place the OPERATE/ALIGN switch to OPERATE, removethe test equipment, properly load the translator output and place the OPERATE/STANDBYswitch to OPERATE.
3143.6 Precorrection Adjustment:Adjustment of the precorrection is accomplished with two potentiometers in the IF Upconverter andeight potentiometers in the Linearizer which should not be realigned unless absolutely necessary.(The IF Upconverter and Linearizer can produce unwanted distortion if adjusted incorrectly.) Thetest equipment which should be available for readjustment of the precorrector is a spectrumanalyzer which provides demodulated video for measurement of sync and intermodulation or awaveform monitor and television demodulator for sync and differential gain measurements.Acquire as much of this test equipment as possible since the precorrection accuracy will dependon equipment versatility. It is assumed that the translator's overall frequency response is correct,allowing the unit to operate with maximum efficiency. 1. To the output of the translator connect the test equipment available for monitoringintermodulation, sync amplitude and differential gain. 2. Remove the four screws on the front panel of the 20W Exciter drawer, pull out the drawer,and remove its top cover. Insure switch S1 of the IF Upconverter is in the ON (right)position and S1 of the Linearizer is in the ON position. 3. Place the translator in operation with the system providing its rated output. After demodu-lating video, slowly adjust R9 and R4 of the IF Upconverter and/or R37, R38, R39, R40,R10, R11, R21 and R22 of the Linearizer for 100% horizontal sync. 4. While looking at the spectral waveform, adjust R4 and R9 of the IF Upconverter and/or R10,R11, R21, R22, R37, R38, R39, and R40 of the Linearizer for minimum in-band intermodu-lation products. This can be accomplished using a modulated ramp video signal and100kHz resolution bandwidth on the spectrum analyzer. 5. Check and, if necessary, correct the translator's output power with the front panel POWERADJUST. 6. Repeat steps #3 through #5 to find the appropriate trade-off for 100% horizontal sync andminimum in-band intermodulation products. 7. Reinstall the top cover to the 20W Exciter drawer, slide the drawer back into the cabinet,secure it, remove the test equipment, and properly load the translator output beforereactivation.3.7 Control Board Setup:The TU1000F V/U CONTROL BOARD (A5PC1) circuit allows the fault voltages to be balancedpreventing fault indications due to gain variations in the 300W Amplifier modules. To set up theCONTROL BOARD the translator must have four 300W amplifier assemblies in good workingcondition. 1. To set CONTROL BOARD, turn off the translator, remove the four screws on the FrontPanel (A5) and pull the panel out.
315 2. Make sure the board is properly fastened to the panel and both dc plugs properly connected.Turn the four potentiometers at the top of the board (R58, R60, R62, and R64) fullyclockwise. 3. Place the translator into operation. Make sure the translator is providing 1000W peak visual(100% on the % RF POWER meter) with a 0% APL video signal and proper depth ofmodulation. 4. Using a voltmeter, check the voltages at test points TP1, TP2, TP3, and TP4. (NOTE: TP5is a ground point.) Note which test point has the lowest voltage. 5. Place the voltmeter on the test point with the lowest voltage as noted in the previous step.Adjust the corresponding potentiometer to reduce this voltage by 0.25V to 0.5V. (R58corresponds to TP1, R60 to TP2, R62 to TP3, and R64 to TP4.) 6. Adjust the remaining three potentiometers so that the voltage of the corresponding test pointis within ±0.1V of the voltage set in step #5. 7. Disconnect the voltmeter and replace the Front Panel, securing it properly.
3163.8 Remote Monitor Signal Levels:This table lists the signal type and levels provided on the REMOTE MONITOR 25-pin cabinetconnector (J4).NAME PIN I/O TTL TYPICAL LEVEL(VOLTS)FWD POWER 18 O +5REFL POWER 19 O 0RF ENABLE 23 O X +5REMOTE ON/OFF 24 I X +5REMOTE VSWR OVLD RESET 20 I X +5PS FAULT AMPL 1 6 O X +5PS FAULT AMPL 2 7 O X +5PS FAULT AMPL 3 8 O X +5PS FAULT AMPL 4 9 O X +5I SENSE AMPL 1 10 O +4.5I SENSE AMPL 2 11 O +4.5I SENSE AMPL 3 12 O +4.5I SENSE AMPL 4 13 O +4.5THERM OVLD AMPL 1 15 O X 0THERM OVLD AMPL 2 14 O X 0THERM OVLD AMPL 3 16 O X 0THERM OVLD AMPL 4 17 O X 0+5V POWER SUPPLY 2 O +5+15V POWER SUPPLY 3 O +1515V POWER SUPPLY 4 O 15+28V POWER SUPPLY 5 O +28GND 1, 25 0
S 13.9 Spare Modules and Components:The following contains the description, vendor, part number, and designator of each module foundin the TU1000F V/U Translator which EMCEE considers to be essential bench-stock items. Thesemodules should be available to the technician at all times.TU1000F V/UINTERCONNECTION DIAGRAM 40386002DESCRIPTION VENDOR/PART # DESIGNATORFans 10" 560CFM 220Vac EMCEE/4C829 B1, B2Control Board EMCEE/40386014-1 A5/PC1Splitter/Combiner EMCEE/40367291-1 CP1, CP2Metering Detector EMCEE/60386050-1 A5/A7DUAL 300W UHF AMPLIFIER INTERCONNECTION DIAGRAM 403860003DESCRIPTION VENDOR/PART # DESIGNATORFans 4.5" 106CFM 220Vac EMCEE/A30135-10 A3B1, A3B2,A4B1, A4B2300W UHF Amplifier EMCEE/40386007-1 A3A1, A3A2,A4A1, A4A2Status Display EMCEE/20386107-1 A3PC1, A4PC1+28V Power Supply TODD/SPF-750-28 A3PS1, A3PS2,A4PS1, A4PS2
S 2TU20F EXCITER INTERCONNECTION DIAGRAM 40383113DESCRIPTION VENDOR/PART # DESIGNATORLinearizer EMCEE/60367083-1 A2A6IF Upconverter EMCEE/70383030-1 A2A12 Watt UHF Amplifier EMCEE/70367080-1 A2A220 Watt UHF Amplifier EMCEE/80383011-1 A2A3UHF Synthesizer EMCEE/60367103-1 A2A4A1Reference Oscillator EMCEE/60368055-1 A2A4A2Metering Detector EMCEE/60368050-1 A2A5+28V Power Supply TODD/SC28-9 A2PS1±15V/+5V Power Supply Deltron/W300A A2PS2Control Board EMCEE/80383018-1 A2PC1Contactor Telemecanique/LP1-EC03 A2K1Voltage Regulator Motorola/MC7812CT A2U1Fans 4.5" 106CFM 220Vac EMCEE/A30135-10 A2B1, A2B2
S 3RECEIVER DRAWER (A1) SPARE MODULES LISTINTERCONNECTION DIAGRAM 30383094 (OSC/MULT)DESCRIPTION VENDOR/PART # DESIGNATORLimiter/Output AGC Control EMCEE/B331-36-1 PC1Automatic-On EMCEE/B331-46-1 PC2IF AGC Amplifier EMCEE/B331-42-1 A3IF Amplifier with SAW Filter EMCEE/B331-27-1 A2Downconverter/Preamplifier EMCEE/B331-47-1 A1+25V Power Supply EMCEE/B326-17-1 PS1PC1±15V, ±5V Power Supply EMCEE/70326117 PS1PC2Oscillator Vectron/CD254D57 G1*** SELECT APPROPRIATE MULTIPLIER AND FILTER ***VHF Bandpass Filter CH 2-6 EMCEE/A280-90-2 FL1VHF Bandpass Filter CH 7-13 EMCEE/A280-90-1 FL1UHF Bandpass Filter CH 14-69 EMCEE/ P/LC331-218-1 FL1X2 Multiplier EMCEE/B280-76-1 A4X4 Multiplier EMCEE/B331-19-1 A4X16 Multiplier EMCEE/70367248 A4
S 4RECEIVER DRAWER (A1) SPARE MODULES LISTINTERCONNECTION DIAGRAM 30383104 (SYNTH)DESCRIPTION VENDOR/PART # DESIGNATORLimiter/Output AGC Control EMCEE/B331-36-1 PC1Automatic-On EMCEE/B331-46-1 PC2IF AGC Amplifier EMCEE/B331-42-1 A3IF Amplifier with SAW Filter EMCEE/B331-27-1 A2Downconverter/Preamplifier EMCEE/B331-47-1 A1+25V Power Supply EMCEE/B326-17-1 PS1PC1±15V, ±5V Power Supply EMCEE/70326117 PS1PC2Reference Oscillator EMCEE/60368055-1 A4A2*** SELECT APPROPRIATE SYNTHESIZER AND FILTER ***VHF Bandpass Filter CH 2-6 EMCEE/A280-90-2 FL1VHF Bandpass Filter CH 7-13 EMCEE/A280-90-1 FL1UHF Bandpass Filter CH 14-69 EMCEE/ P/LC331-218-1 FL1VHF Synthesizer High Band EMCEE/60367103-2 A4A1VHF Synthesizer Low Band EMCEE/60367103-3 A4A1UHF Synthesizer EMCEE/60367103-1 A4A1

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