Cypress Semiconductor 3136 This product is a Bluetooth wireless EZ-BLE Module with HomeKit User Manual CYBT 013033 01 EZ BT Module

Cypress Semiconductor This product is a Bluetooth wireless EZ-BLE Module with HomeKit CYBT 013033 01 EZ BT Module

UserManual.wiki >

Cypress Semiconductor >

3136 User Manual >

Use rmanual_CYBLE-473142-01

Contents

Use rmanual_CYBLE-473142-01

Document Number: CYBLE-473142-01 Preliminary Page 2 of 34CYBLE-473142-01ContentsOverview............................................................................ 3Functional Block Diagram ........................................... 3Module Description...................................................... 3Pad Connection Interface ................................................ 5Recommended Host PCB Layout ................................... 6Module Connections ........................................................ 7Connections and Optional External Components ....... 7Power Connections (VDD) .......................................... 7External Reset (XRES)................................................ 8UART Connections...................................................... 8External Component Recommendation ...................... 8Critical Components List ........................................... 10Antenna Design......................................................... 10Bluetooth Baseband Core ............................................. 11Bluetooth Low Energy ............................................... 11Power Management Unit................................................ 12RF Power Management ............................................ 12Host Controller Power Management ......................... 12BBC Power Management.......................................... 12Microprocessor Unit....................................................... 13Floating Point Unit..................................................... 13On-Chip Flash ........................................................... 13OTP........................................................................... 13External Reset........................................................... 13Integrated Radio Transceiver ........................................ 14Transmitter Path........................................................ 14Digital Modulator ....................................................... 14Power Amplifier ......................................................... 14Receiver Path............................................................ 14Digital Demodulator and Bit Synchronizer................. 14Receiver Signal Strength Indicator............................ 14Calibration ................................................................. 15Internal LDO Regulator ............................................. 15Peripheral Transport Unit .............................................. 15UART Interface.......................................................... 15Peripheral UART Interface ........................................ 16ADC Port.......................................................................... 16PWM................................................................................. 16Triac Control ................................................................... 17Security Engine .............................................................. 17Electrical Characteristics............................................... 18Core Buck Regulator................................................. 19Digital LDO................................................................ 20RF LDO ..................................................................... 21Digital I/O Characteristics.......................................... 22Current Consumption ................................................ 22RF Specifications ........................................................... 23Timing and AC Characteristics ..................................... 24UART Timing............................................................. 24Environmental Specifications ....................................... 25Environmental Compliance ....................................... 25RF Certification.......................................................... 25Safety Certification .................................................... 25Environmental Conditions ......................................... 25ESD and EMI Protection ........................................... 25Regulatory Information.................................................. 26FCC........................................................................... 26Innovation, Science and Economic Development (ISED) Canada Certification......................................................... 27European Declaration of Conformity ......................... 28Packaging........................................................................ 29Ordering Information...................................................... 31Acronyms........................................................................ 32Document Conventions ................................................. 32Units of Measure ....................................................... 32Document History Page................................................. 33Sales, Solutions, and Legal Information ...................... 34Worldwide Sales and Design Support....................... 34Products .................................................................... 34PSoC® Solutions ...................................................... 34Cypress Developer Community................................. 34Technical Support ..................................................... 34

Document Number: CYBLE-473142-01 Preliminary Page 3 of 34CYBLE-473142-01OverviewFunctional Block DiagramFigure 1 illustrates the CYBLE-473142-01 functional block diagram.Figure 1. Functional Block DiagramModule DescriptionThe CYBLE-473142-01 module is a complete module designed to be soldered to the applications main board. Module Dimensions and DrawingCypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selectionswill still guarantee that all mechanical specifications and module certifications are maintained. Any changes to the current BOM forthe CYBLE-473142-01 will not be made until approval is provided by the end customer for this product. The CYBLE-473142-01 willbe held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 4. All dimensions are in millimeters (mm).Table 1. Module Design DimensionsSee Figure 2 for the mechanical reference drawing for CYBLE-473142-01.Dimension Item SpecificationModule dimensions Length (X) 14.70 ± 0.15 mmWidth (Y) 20.00 ± 0.15 mmAntenna location dimensions Length (X) 14.70 mmWidth (Y) 4.80 mmPCB thickness Height (H) 0.80 ± 0.10 mmShield height Height (H) 1.80 mmMaximum component height Height (H) 0.60 mm typicalTotal module thickness (bottom of module to highest component) Height (H) 2.60 mm typical

Document Number: CYBLE-473142-01 Preliminary Page 4 of 34CYBLE-473142-01Figure 2. Module Mechanical DrawingBottom View (Seen from Bottom)Side ViewTop View (See from Top)Notes4. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see “Recommended Host PCB Layout” on page 6.5. The CYBLE-473142-01 includes castellated pad connections, denoted as the circular openings at the pad location above.

Document Number: CYBLE-473142-01 Preliminary Page 5 of 34CYBLE-473142-01Pad Connection InterfaceAs shown in the bottom view of Figure 2 on page 4, the CYBLE-473142-01 has seven main connections that are connected to thehost board via castellated solder pads (“CSP”). The CYBLE-473142-01 also includes additional solder pad connections (“SP”) usedfor debug or testing on the bottom side of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensionsof the CYBLE-473142-01 module. Figure 3. Solder Pad Dimensions (Seen from Bottom)To maximize RF performance, the host layout should follow these recommendations:1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 4) mustcontain no ground or signal traces. This keep out area requirement applies to all layers of the host board. 2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB traceantenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Pleaserefer to AN96841 for module placement best practices.3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module PCB trace antennamay contain an additional keep out area, where no grounding or signal traces are contained. The keep out area applies to all layersof the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBLE-473142-01 PCB Trace AntennaTable 2. Connection DescriptionName Connections Connection Type Pad Length Dimension Pad Width Dimension Pad PitchCSP 7 Castellated Solder Pads 2.00 mm 1.30 mm 2.00 mmSP 7 Solder Pads 0.65 mm (Radius) 0.65 mm (Radius) N/ACastellated Solder Pad (CSP) and Solder Pad (SP) Connection (Seen from Bottom)Optional Host PCB Keep Out Area Around Chip Antenna

Document Number: CYBLE-473142-01 Preliminary Page 6 of 34CYBLE-473142-01Recommended Host PCB LayoutFigure 5 (Dimensioned) and Figure 6 (Relative to Origin) provide the recommended host PCB layout pattern for theCYBLE-473142-01. Pad length of 1.27 mm (0.655 mm from center of the pad on either side) shown in Figure 6 is the minimumrecommended host pad length. All dimensions are in millimeters. Figure 5. CYBLE-473142-01 Host Layout (Dimensioned) Figure 6. CYBLE-473142-01 Host Layout (Relative to Origin)Top View (Seen on Host PCB)Top View (Seen on Host PCB)

Document Number: CYBLE-473142-01 Preliminary Page 7 of 34CYBLE-473142-01Module ConnectionsTab le 3 details the solder pad connection definitions and available functions for each connection pad. Table 3 lists the solder pads onthe CYBLE-473142-01, the silicon device pin, and denotes what functions are available for each solder pad. Table 3 also lists theprimary/intended function for each solder pad for the application this module was specifically designed for.Connections and Optional External ComponentsPower Connections (VDD)The CYBLE-473142-01 contains one power supply connection, VDD.VDD accepts a supply input of 3.30 V. Tabl e 9 provides this specification. The maximum power supply ripple for this power connectionis 300 mV, as shown in Table 9. Considerations and Optional Components for Brown Out (BO)ConditionsPower supply design must be completed to ensure that the CYBLE-473142-01 module does not encounter a Brown Out condition,which can lead to unexpected funcitonality, or module lock up. A Brown Out condition may be met if power supply provided to themodule during power up or reset is in the range shown below: VIL ≤ VDD ≤ VIHRefer to Table 13 for the VIL and VIH specifications. System design should ensure that the condition above is not encountered when power is removed from the system. In the event thatthis cannot be guaranteed (i.e. battery installation, high value power capacitors with slow discharge), it is recommended that anexternal voltage detection device be used to prevent the Brown Out voltage range from occuring during power removal. Please referto Figure 7 for the recommended circuit design when using an external voltage detection IC.Table 3. Solder Pad Connection Definitions Pad Num-ber Pad Name UART PWM GPIO Primary Function1 VDD Power Supply Input (3.30 V) Power Supply Input2 GND Ground Connection Ground Connection3PWM1 33PWM R, G, B, or W Function4PWM2 33PWM R, G, B, or W Function5PWM3 33PWM R, G, B, or W Function6PWM4 33PWM R, G, B, or W Function7ADC ADC Input8PUART_TX 3(PUART_TXD) Peripheral UART TXD9PUART_RX 3(PUART_RXD) 33Peripheral UART RXD10 XRES External Reset Hardware Connection Input External Reset (Active Low)11 UART_RXD 3(UART_RXD) UART RXD12 UART_TXD 3(UART_TXD) UART TXD13 UART_CTS 3(UART_CTS) UART CTS14 UART_RTS 3(UART_RTS) UART RTSGND GND Ground Connection Ground ConnectionsMust be soldered to host boardGND GND Ground Connection

Document Number: CYBLE-473142-01 Preliminary Page 8 of 34CYBLE-473142-01Figure 7. Reference Circuit Block Diagram for External Voltage Detection ICIn the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling themodule will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potential cause issuesthat cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition. External Reset (XRES)The CYBLE-473142-01 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. Thisaction can also be envoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal,which is an input to the CYBLE-473142-01 module (solder pad 3). The CYBLE-473142-01 module does not require an external pull-upresistor on the XRES input During power on operation, the XRES connection to the CYBLE-473142-01 is required to be held low 50 ms after the VDD powersupply input to the module is stable. This can be accomplished in the following ways: nThe host device should connect a GPIO to the XRES of Cypress CYBLE-473142-01 module and pull XRES low until VDD is stable.XRES is recommended to be released 50 ms after VDD is stable.nIf the XRES connection of the CYBLE-473142-01 module is not used in the application, a 0.33 uF capacitor may be connected tothe XRES solder pad of the CYBLE-473142-01 in order to delay the XRES release. The capacitor value for this recommendedimplementation is approximate, and the exact value may differ depending on the VDD power supply ramp time of the system. Thecapacitor value should result in an XRES release timing of 50 ms after VDD stability. nThe XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable.Refer to Figure 10 on page 14 for XRES operating and timing requirements during power on events.UART ConnectionsFor full UART functionality, all UART signals must be connected to the Host device. If full UART functionality is not being used, andonly UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS andCTS: nUART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on. nUART CTS: Must by pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to themodule. External Component RecommendationPower Supply CircuitryIt is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite beadbetween the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positionedas close as possible to the module pin connection. If used, the recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).Apple MFi Authentication Coprocessor InterfaceThe CYBLE-473142-01 comes with an integrated MFi authentication co-processor. No additoinal connections are required to be madeto the module to enable Apple HomeKit functionality. All connections required are internally routed on the module PCB.

Document Number: CYBLE-473142-01 Preliminary Page 9 of 34CYBLE-473142-01Figure 8 illustrates the CYBLE-473142-01 schematic.Figure 8. CYBLE-473142-01 Schematic Diagram

Document Number: CYBLE-473142-01 Preliminary Page 10 of 34CYBLE-473142-01Critical Components ListTab le 4 details the critical components used in the CYBLE-473142-01 module.Table 4. Critical Component ListAntenna DesignTab le 5 details the PCB trace antenna used in the CYBLE-473142-01 module. Table 5. Trace Antenna SpecificationsComponent Reference Designator DescriptionAuthentication Co-Processor U1 Apple Authentication Co-processorSilicon U2 40-pin QFN BLE Silicon Device - CYW20719 B1 SiliconPA/LNA U3 17-pin QFN - Skyworks RFX2401CCrystal Y1 24.000 MHz, 12PFItem DescriptionFrequency Range 2402 – 2480 MHzPeak Gain –0.5 dBi maximum

Document Number: CYBLE-473142-01 Preliminary Page 11 of 34CYBLE-473142-01Bluetooth Baseband CoreThe Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,handles data flow control, schedules TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data intobaseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, itindependently handles host controller interface (HCI) event types, and HCI command types.The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of theTX/RX data before sending over the air:nSymbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),data decryption, and data dewhitening in the receiver.nData framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in thetransmitter.Bluetooth Low EnergyThe CYBLE-473142-01 supports single-mode Bluetooth LE operation. The CYBLE-473142-01 supports all Bluetooth 4.2 and legacyLE features, with the following benefits: nLE data packet length extensionnLE secure connections nLink layer privacynEnables Bluetooth Smart sensors to access the Internet directly via IPv6/6LoWPANLink Control LayerThe link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).This layer consists of the command controller that takes commands from the software, and other controllers that are activated orconfigured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth® LinkController. nMajor states: pStandby pConnection

Document Number: CYBLE-473142-01 Preliminary Page 12 of 34CYBLE-473142-01Power Management UnitThe Power Management Unit (PMU) provides power management features that can be invoked through power management registersor packet handling in the baseband core. This section contains descriptions of the PMU features.Figure 9. Power Management Unit of CYW20719RF Power ManagementFigure 9 shows the CYBLE-473142-01 power management unit (PMU) block diagram that is contained in the CYW20719 silicondevice. The CYW20719 includes an integrated buck regulator, a bypass LDO, a capless LDO, and an additional 1.2 V LDO for RF.Host Controller Power ManagementPower is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls thedisabling of the on-chip regulator when in HIDOFF (deep sleep) mode.BBC Power ManagementThere are several low-power operations for the BBC:nPhysical layer packet handling turns RF on and off dynamically within packet TX and RX.nBluetooth-specified low-power connection mode. While in these low-power connection modes, the CYBLE-473142-01 runs on theLow Power Oscillator and wakes up after a predefined time period.The CYBLE-473142-01 automatically adjusts its power dissipation based on user activity. It supports the following power modes:nActive modenIdle modenSleep mode (not enabled for the specific application the CYBLE-473142-01 is used in)nHIDOFF (deep sleep) mode The CYBLE-473142-01 transitions to the next lower state after a programmable period of user inactivity. When user activityresumes, the CYBLE-473142-01 immediately enters Active mode.In HIDOFF mode, the CYBLE-473142-01 baseband and core are powered off by disabling power to VDDC_OUT and PAVDD. TheVDDO domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chippower consumption and is used for extended periods of inactivity.

Document Number: CYBLE-473142-01 Preliminary Page 13 of 34CYBLE-473142-01Microprocessor UnitThe CYBLE-473142-01 microprocessor unit runs software from the link control (LC) layer up to the host controller interface (HCI).The microprocessor is a Cortex®-M4 32-bit RISC processor with embedded ICE-RT debug and serial wire debug (SWD) interfaceunits. The microprocessor also includes 2 MB of ROM memory for program storage and 512 KB of RAM for data scratch-pad.The internal ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. Atpower-up, the lower layer protocol stack is executed from the internal ROM.External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. The devicealso supports the integration of user applications and profiles. Patches and applications can be stored in on-chip flash.Floating Point UnitThe CYBLE-473142-01 includes the CM4 single precision IEEE-754 compliant floating point unit. For additional details, see the Cor-tex-M4 manual.On-Chip FlashThe silicon device used in the CYBLE-473142-01 module includes 1 MB of on-chip flash. This flash can be used for direct programexecution or for non-volatile data. Typical usage for the on-chip flash includes:nChip configurationnPatchesnPeer addresses and link keysnApplication codenApplication non-volatile datanProduct informationOTPThe CYBLE-473142-01 includes 2 KB of one-time programmable (OTP) memory. This memory can be used by the factory to storeproduct specific information. Note: Use of OTP requires a 3 V supply to be present at all times.External ResetAn external active-low reset signal, XRES, can be used to put the CYBLE-473142-01 in the reset state. An external voltage detectorreset IC with 50 ms delay is needed on the XRES. The XRES should be released only after the VDDO supply voltage level has beenstabilized for 50 ms.

Document Number: CYBLE-473142-01 Preliminary Page 14 of 34CYBLE-473142-01Figure 10. Reset TimingIntegrated Radio TransceiverThe CYBLE-473142-01 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth wireless systems. It has beendesigned to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unli-censed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the requirements to provide thehighest communication link quality of service.Transmitter PathThe CYBLE-473142-01 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISMband.Digital ModulatorThe digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizesany frequency drift or anomalies in the modulation characteristics of the transmitted signal.Power AmplifierThe CYBLE-473142-01 has an integrated power amplifier (PA) on the silicon device as well as a high power external power amplifier(PA) integrated on the module. The total output power that this module is designed to achieve is +8 dBm.Receiver PathThe receiver path uses a low IF scheme to down convert the received signal for demodulation in the digital demodulator and bit syn-chronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in thenoisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBLE-473142-01 to beused in most applications without off-chip filtering.Digital Demodulator and Bit SynchronizerThe digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit syn-chronization algorithm.Receiver Signal Strength IndicatorThe radio portion of the CYBLE-473142-01 provides a receiver signal strength indicator (RSSI) to the baseband. This enables thecontroller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determinewhether the transmitter should increase or decrease its output power.

Document Number: CYBLE-473142-01 Preliminary Page 15 of 34CYBLE-473142-01CalibrationThe CYBLE-473142-01 radio transceiver features a self-contained automated calibration scheme. No user interaction is requiredduring normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching net-work, and amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes processand temperature variations into account, and it takes place transparently during normal operation and hop setting times.Internal LDO RegulatorThe CYBLE-473142-01 has an integrated 1.2 V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO reg-ulator operates from a 1.425 V to 3.63 V input supply with a 30 mA maximum load current.Peripheral Transport UnitUART InterfaceThe CYBLE-473142-01 includes a UART interface for factory programming as well as when operating as a BT HCI device in a sys-tem with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baudrates from 9600 bps to 6 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via avendor-specific UART HCI command. The CYBLE-473142-01 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to sup-port enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2kbaud.The UART clock default setting is 24 MHz. The baud rate of the CYBLE-473142-01 UART is controlled by two values. The first is aUART clock divisor (set in the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rateadjustment (set in the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of eachbit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can beinserted into the end of each bit time. Table 6 contains example values to generate common baud rates with a 24 MHz UART clock.Tab le 7 contains example values to generate common baud rates with a 48 MHz UART clock.Table 6. Common Baud Rate Examples, 24 MHz ClockBaud Rate (bps) DHBR DLBR Mode Error (%)3M 0xFF 0xF8 High rate 0.002M 0XFF 0XF4 High rate 0.001.5M 0X00 0XFF Normal 0.001M 0x44 0xFF Normal 0.00921600 0x55 0xFF Normal 0.16460800 0x22 0xFD Normal 0.16230400 0x44 0xFA Normal 0.16115200 0x00 0xF3 Normal 0.1638400 0x01 0xD9 Normal 0.00Table 7. Common Baud Rate Examples, 48 MHz ClockBaud Rate (bps) High Rate Low Rate Mode Error (%)6M 0xFF 0xF8 High rate 0.004M 0xFF 0xF4 High rate 0.003M 0x0 0xFF Normal 0.002M 0x44 0xFF Normal 0.001.5M 0x00 0xFE Normal 0.001M 0x00 0xFD Normal 0.00921600 0x22 0xFD Normal 0.16460800 0x44 0xFA Normal 0.16

Document Number: CYBLE-473142-01 Preliminary Page 16 of 34CYBLE-473142-01Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allowsthe host to adjust the contents of the baud rate registers.The CYBLE-473142-01 UART operates correctly with the host UART as long as the combined baud rate error of the two devices iswithin ±5%.Peripheral UART InterfaceThe CYBLE-473142-01 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed throughthe optional I/O ports, which can be configured individually and separately for each functional pin. ADC PortThe ADC block is a single switched-cap Σ-Δ ADC core for audio and DC measurement. It operates at the 12 MHz clock rate. Theinternal bandgap reference has ±5% accuracy without calibration. Different calibration and digital correction schemes can be appliedto reduce ADC absolute error and improve measurement accuracy in DC mode.PWMThe CYBLE-473142-01 has five PWMs. The PWM module consists of the following:nPWM1–5. Each of the five PWM channels contains the following registers:p16-bit initial value register (read/write)p16-bit toggle register (read/write)p16-bit PWM counter value register (read)nPWM configuration register shared among PWM1–5 (read/write). This 18-bit register is used:pTo configure each PWM channelpTo select the clock of each PWM channel pTo change the phase of each PWM channelFigure 11 shows the structure of one PWM.230400 0x0 0xF3 Normal 0.16115200 0x1 0xE6 Normal –0.0857600 0x1 0xCC Normal 0.0438400 0x11 0xB2 Normal 0.0019200 0x22 0x64 Normal 0.00Table 7. Common Baud Rate Examples, 48 MHz Clock (continued)Baud Rate (bps) High Rate Low Rate Mode Error (%)

Document Number: CYBLE-473142-01 Preliminary Page 17 of 34CYBLE-473142-01Figure 11. PWM Block DiagramTriac ControlThe CYBLE-473142-01 includes hardware support for zero-crossing detection and trigger control for up to four triacs. TheCYBLE-473142-01 detects zero-crossing on the AC zero detection line and uses that to provide a pulse that is offset from the zerocrossing. This allows the CYBLE-473142-01 to be used in dimmer applications, as well as any other applications that require a con-trol signal that is offset from an input event.The zero-crossing hardware includes an option to suppress glitches.Security EngineThe CYBLE-473142-01 includes a hardware security accelerator which greatly decreases the time required to perform typical secu-rity operations. Access to the hardware block is provided via a firmware interface (see firmware documentation for details).Thiesecurity engine includes:nPublic key acceleration (PKA) cryptographynAES-CTR/CBC-MAC/CCM accelerationnSHA2 message hash and HMAC accelerationnRSA encryption and decryption of modulus sizes up to 2048 bitsnElliptic curve Diffie-Hellman in prime field GF(p)nGeneric modular math functions

Document Number: CYBLE-473142-01 Preliminary Page 18 of 34CYBLE-473142-01Electrical CharacteristicsNote: All voltages listed in Table 8 are referenced to VDD.Tab le 9 shows the power supply characteristics for the range TJ = 0°C to 125°C.Table 8. Absolute Maximum VoltagesRequirement ParameterSpecificationUnitMinimum Nominal MaximumAmbient Temperature of Operation –30 25 105 °CStorage temperature –30 – 110 °CESD Tolerance HBM (Silicon) –2000 – 2000 VESD Tolerance MM (Silicon) –100 – 100 VESD Tolerance CDM (Silicon) –500 – 500 VLatch-up (Silicon) – 200 – mATable 9. Power Supply SpecificationsParameter Conditions Min. Typical Max. UnitVDD input Module Input 3.0 3.3 3.6 VVDD Ripple Module Input – – 100 mVVBAT Input Internal to Module (not accessible) 1.62 3.3 3.6 VPMU turn-on time VBAT is ready. – – 300 μs

Document Number: CYBLE-473142-01 Preliminary Page 19 of 34CYBLE-473142-01Core Buck RegulatornMinimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature,and aging.nMaximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes anydecoupling capacitors connected at the load side, if any.Table 10. Core Buck Regulator (Internal to Module)Parameter Conditions Min. Typ. Max. UnitInput supply voltage DC, VBAT DC voltage range inclusive of disturbances 2.1 3.3 3.63 VCBUCK output current LPOM only – – 65 mAOutput over-current limit Peak inductor current TBD – – mAOutput voltage range Programmable, 30mV/stepdefault = 1.2V (bits=0000)1.2 1.2 1.5 VOutput voltage DC accuracy Includes load and line regulation:• Before trimming• After trimming–4–2–+4+2%%LPOM ripple voltage, static Measured with 20 MHz bandwidth limit, static load. Max ripple based on VBAT=3V, Vout=1.2VInductor:0806 inch-size, Tmax=1 mm, 2.2 μH ±25%, DCR=114 mW ±20%, ACR<1W (for frequency <1 MHz)Capacitor:1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor + board total-ESR < 20 mW– – 30 mVppLPOM efficiency (high load) 10–50 mA load current, Vout=1.2V, Vbat=3V @25°CInductor:0806 inch-size, Tmax=1 mm,2.2 μH ±25%, DCR=114 mW ±20%, ACR<1W (for frequency<1 MHz)Capacitor:1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor +board total-ESR < 20 mW–85–%LPOM efficiency (low load) 1–5 mA load current, Vout=1.2V, Vbat=3V @25°CInductor:0806 inch-size, Tmax=1 mm,2.2 μH ±25%, DCR=114 mW ±20%, ACR<1W (for frequency<1 MHz)Capacitor:1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor +board total-ESR < 20 mW–80–%Startup time see Table 11 on page 20.––––External inductor L 2.2 μH ±25%, DCR=114 mW ±20%, ACR<1W (for frequency<1 MHz)–2.2–μHExternal output capacitor, Cout 1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor +board total-ESR < 20 mW0.7 1 1.1 μFExternal input capacitor, Cin For SR_VDDBAT pinCeramic, X5R, 0402, ESR<30 mW at 4 MHz, +/-20%, 6.3V, 4.7 μF0.7 4.7 5.64 μFInput supply voltage ramp-up time 0 to 3.3V 40 – – μs

Document Number: CYBLE-473142-01 Preliminary Page 20 of 34CYBLE-473142-01Digital LDOTable 11. Digital LDO (Internal to Module)Parameter Conditions Min. Typ. Max. UnitInput supply voltage, Vin Minimum Vin=Vo+0.12V requirement must be met under maximum load. 1.2 1.2 1.6 VNominal output voltage,Vo Internal default bit setting – 1.1 – VOutput voltage programmability RangeStep sizeAccuracy at any step (including line/load regulation) before trimmingAccuracy at any step (including line/load regulation) after trimming0.9––4–2–10––1.25–+4+2VmV%%Dropout voltage At maximum load – – 120 mVOutput current DC load 0.211. By default, an internal loading of ~0.2 mA resides inside the LDO. This is to ensure the LDO is stable with zero loading from the core. After the core is up, digital logic can disable this internal loading by setting i_ldo_cntl<8:7> to 00.–40mAOutput loading capacitor Internal, including the decoupling capacitor to be placed next to the load and the equivalent loading capacitor by the core.4–10nFQuiescent current At no load, excluding main bandgap Iq – 90 120 μALine regulation Vin from (Vo+0.12V) to 1.5V; 40 mA load – – 5 mV/VLoad regulation Load from 1 mA to 25 mA; Vin (Vo+0.12V) – 0.025 0.045 mV/mALeakage current In full power-down mode or bypass mode:• Junction temperature: 25°C• Junction temperature: 125°C––0.051.10.25.0μAμAPSRR @1 kHz, Vin, Vo+0.12VOutput cap of 4 nF~10 nF40 – – dBPMU startup time VBAT is up and steady. Time from HID_OFF falling edge to DIGLDO reaching 99% of Vo. – 100 – μsLDO turn-on time LDO turn-on time when balance of chip is up – – 22 μsExternal input capacitor Only use an external input capacitor at VDD_DIGLDO pin if it is not supplied from CBUCK output. –12.2μF

Document Number: CYBLE-473142-01 Preliminary Page 21 of 34CYBLE-473142-01RF LDOTable 12. RF LDO (Internal to Module)Parameter Conditions Min. Typ. Max. UnitInput supply voltage, Vin Min Vin=Vo+0.15V = 1.35V (for Vo=1.2V)Dropout voltage requirement must be met under maximum load.1.2 1.35 1.5 VNominal output voltage,Vo Internal default bit setting 000 – 1.2 – VOutput voltage programmability RangeStep sizeAccuracy at any step (including line/load regulation) Accuracy at any step (including line/load regulation) after trimming1.1––4–2–25––1.275–+4+2VmV%%Dropout voltage At maximum load – – 150 mVOutput current TBD 0.1 – 25 mAQuiescent current No load – 44 – μALine regulation Vin from (Vo+0.15V) to 1.5V; 25 mA load – – 5.5 mV/VLoad regulation Load from 1 mA to 25 mA; Vin ≥ (Vo+0.15V) – 0.025 0.045 mV/mALoad step error Load step from 1 mA–25 mA in 1 μs and 25 mA–1 mA in 1μs; Vin(Vo+0.15V); Co=2.2 μF––35mVLeakage current Power-down junction temperature: 85°C – – 10 μAOutput noise @30 kHz, 25 mA load, Co= 2.2 μF @100 kHz, 25 mA load, Co= 2.2 μF––6035nV/√HznV/√HzPSRR @1kHz, Input > 1.35V, Co= 2.2 μF, Vo=1.2V 20 – – dBLDO turn-on time LDO turn-on time when balance of chip is up – 140 180 μsIn-rush current Vin=Vo+0.15V to 1.5V, Co=2.2 μF, no load – – 100 mAExternal output capacitor, Co Total ESR (trace/cap): 5 m–240 mW 0.5 2.2 4.7 μFExternal input capacitor Only use an external input capacitor at VDD_DIGLDO pin if it is not supplied from CBUCK output. –12.2μFNote: Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.

Document Number: CYBLE-473142-01 Preliminary Page 22 of 34CYBLE-473142-01Digital I/O CharacteristicsCurrent ConsumptionIn Table 14, current consumption measurements are taken at VBAT with the assumption that VBAT is connected to VDDIO andLDOIN. Module current consumption measurements are taken at VDD.Table 13. Digital I/O CharacteristicsCharacteristics Symbol Minimum Typical Maximum UnitInput low voltage (VDD = 3.3V) VIL ––0.8VInput high voltage (VDD = 3.3V) VIH 2.0 – – VOutput low voltage VOL ––0.4VOutput high voltage VOH VDD – 0.4V – – VInput low current IIL ––1.0μAInput high current IIH ––1.0μAOutput low current (VDD = 3.3V, VOL = 0.4V) IOL ––2.0mAOutput high current (VDD = 3.3V, VOH = 2.9V) IOH ––4.0mAInput capacitance CIN ––0.4pFTable 14. BLE Current ConsumptionProduct Operational Mode Conditions Typical UnitCYW20719 B1(Silicon)Receiving Receiver and baseband are both operating, 100% ON, silicon only. 5.8 mATransmitting Transmitter and baseband are both operating, 100% ON, silicon only. 5.7 mAPDS 512 KB SRAM memory retention, silicon only. 70 μADeep Sleep 16 KB SRAM memory retention, silicon only. 1 μAHIDOFF Wakeup only from XRES. No SRAM memory retention, silicon only.350 nAConnection, 1-s Avg. Average Power, 1-second connection interval, silicon only. Deep Sleep mode enabled during non-TX/RX17 μAConnection, 4-s Avg. Average Power, 4-second connection interval, silicon only. Deep Sleep mode enabled during non-TX/RX5μACYBLE-473142-01 (Module)Receiving Receiver and baseband are both operating, 100% ON, module. 13.3 mATransmitting Transmitter and baseband are both operating, 100% ON, module. 32.7 mAConnection Average Power, using FW V0.3.6 of actual application 9.0 mAAdvertising Average Power, using FW V0.3.6 of actual application 11.0mA

Document Number: CYBLE-473142-01 Preliminary Page 23 of 34CYBLE-473142-01RF SpecificationsNote: Table 15 and Table 16 apply to single-ended industrial temperatures. Unused inputs are left open.Table 15. Receiver RF SpecificationsParameter Mode and Conditions Min Typ Max UnitReceiver SectionFrequency range – 2402 – 2480 MHzRX sensitivity GFSK, BDR GFSK 0.1% BER, 1 MbpsModule– –93.0 – dBmMaximum input – –20 – – dBmTable 16. Transmitter RF SpecificationsParameter Min Typ Max UnitTransmitter SectionFrequency range 2402 – 2480 MHzClass 2: GFSK Tx power (silicon) – 4 – dBmClass 2: GFSK Tx power (module) – 8 – dBm20 dB bandwidth – 930 1000 kHzFrequency DriftDH1 packet –25 – +25 kHzDH3 packet –40 – +40 kHzDH5 packet –40 – +40 kHzDrift rate –20 20 kHz/50 µsFrequency DeviationAverage deviation in payload(sequence used is 00001111)140 – 175 kHzMaximum deviation in payload(sequence used is 10101010)115 – – kHzChannel spacing – 1 – MHzTable 17. BLE RF SpecificationsParameter Conditions Minimum Typical Maximum UnitFrequency range N/A 2402 – 2480 MHzRx sensitivity11. Dirty Tx is Off.GFSK, BDR GFSK 0.1% BER 0.1% BER, 1 Mbps – –93.0 – dBmTx power N/A – 4 – dBmMod Char: Delta F1 average N/A 225 255 275 kHzMod Char: Delta F2 max22. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.N/A 99.9 – – %Mod Char: Ratio N/A 0.8 0.95 – %

Document Number: CYBLE-473142-01 Preliminary Page 24 of 34CYBLE-473142-01Timing and AC CharacteristicsIn this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.UART TimingFigure 12. UART TimingTable 18. UART Timing SpecificationsReference Characteristics Min. Typ. Max. Unit1 Delay time, UART_CTS_N low to UART_TXD valid. – – 1.50 Bit periods2 Setup time, UART_CTS_N high before midpoint of stop bit. – – 0.67 Bit periods3 Delay time, midpoint of stop bit to UART_RTS_N high. – – 1.33 Bit periods

Document Number: CYBLE-473142-01 Preliminary Page 25 of 34CYBLE-473142-01Environmental SpecificationsEnvironmental ComplianceThis Cypress BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS), Halogen-Free (HF), andREACH directives. The Cypress module and components used to produce this module are RoHS, HF, and REACH compliant.RF CertificationThe CYBLE-473142-01 module is certified under the following RF certification standards:nFCC: WAP3136nISED: 7922A-3136nCESafety CertificationThe CYBLE-473142-01 module complies with the following safety regulations:nUnderwriters Laboratories, Inc. (UL): Filing E331901nCSAnTUVEnvironmental ConditionsTab le 19 describes the operating and storage conditions for the Cypress BLE module.ESD and EMI ProtectionExposed components require special attention to ESD and electromagnetic interference (EMI).A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosurenear the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.Table 19. Environmental Conditions for CYBLE-473142-01Description Minimum Specification Maximum SpecificationOperating temperature −30 °C 105 °COperating humidity (relative, non-condensation) 5% 85%Thermal ramp rate – 10 °C/minuteStorage temperature –40 °C 110 °CStorage temperature and humidity – 110 °C at 85%ESD: Module integrated into system Components[6] –15 kV Air2.0 kV ContactNote6. This does not apply to the RF pins (ANT).

Document Number: CYBLE-473142-01 Preliminary Page 26 of 34CYBLE-473142-01Regulatory InformationFCCFCC NOTICE:The device CYBLE-473142-01 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitterapproval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This devicemay not cause harmful interference, and (2) This device must accept any interference received, including interference that may causeundesired operation.CAUTION:The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved byCypress Semiconductor may void the user's authority to operate the equipment.This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipmentgenerates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may causeharmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipmentoff and on, the user is encouraged to try to correct the interference by one or more of the following measures:nReorient or relocate the receiving antenna. nIncrease the separation between the equipment and receiver. nConnect the equipment into an outlet on a circuit different from that to which the receiver is connected. nConsult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visiblelabel on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as wellas the FCC Notice above. The FCC identifier is FCC ID: WAP3136.In any case the end product must be labeled exterior with “Contains FCC ID: WAP3136”.ANTENNA WARNING: This device is tested with a standard SMA connector and with the antenna listed in Table 5 on page 10. When integrated in the OEMsproduct, this fixed antenna requires installation preventing end-users from replacing them with non-approved antennas. Any antennanot in Table 5 on page 10 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 foremissions.RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approvedantenna in the previous.The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennasin Table 5 on page 10, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removalinstructions about the integrated radio module is not allowed.The radiated output power of CYBLE-473142-01 with the integrated PCB trace antenna (FCC ID: WAP3136) is far below the FCCradio frequency exposure limits. Nevertheless, use CYBLE-473142-01 in such a manner that minimizes the potential for humancontact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided withtransmitter operating conditions for satisfying RF exposure compliance.

Document Number: CYBLE-473142-01 Preliminary Page 27 of 34CYBLE-473142-01Innovation, Science and Economic Development(ISED) Canada CertificationCYBLE-473142-01 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED)Canada. License: IC: 7922A-3136Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensurecompliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance fromwww.ic.gc.ca.This device has been designed to operate with the antennas listed in Table 5 on page 10, having a maximum gain of -0.5 dBi. Antennasnot included in Table 5 on page 10 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The requiredantenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with anyother antenna or transmitter.ISED NOTICE:The device CYBLE-473142-01 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets therequirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) Thisdevice may not cause harmful interference, and (2) This device must accept any interference received, including interference thatmay cause undesired operation.L'appareil CYBLE-473142-01, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond auxexigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditionssuivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, ycompris les interférences pouvant entraîner un fonctionnement indésirable.ISED INTERFERENCE STATEMENT FOR CANADAThis device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s).Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept anyinterference, including interference that may cause undesired operation of the device.Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte delicence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateurde l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonction-nement.ISED RADIATION EXPOSURE STATEMENT FOR CANADAThis equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should beinstalled and operated with a minimum distance 15mm between the radiator and the operator. Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé. Cet équipementdoit être installé et utilisé avec une distance minimale de 15 mm entre le radiateur et l'opérateur.LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visiblelabel on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well asthe ISED Notice above. The IC identifier is 7922A-3136. In any case, the end product must be labeled in its exterior with "ContainsIC: 7922A-3136".Le fabricant d'équipement d'origine (OEM) doit s'assurer que les exigences d'étiquetage ISED sont respectées. Cela comprend uneétiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Cypress Semiconductor IC approprié pour ce produitainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-3136. En tout cas, le produit final doit être étiqueté dans son extérieuravec "Contient IC: 7922A-3136".

Document Number: CYBLE-473142-01 Preliminary Page 28 of 34CYBLE-473142-01European Declaration of ConformityHereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-473142-01 complies with the essential requirements andother relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive2014, the end-customer equipment should be labeled as follows:All versions of the CYBLE-473142-01 in the specified reference design can be used in the following countries: Austria, Belgium,Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

Document Number: CYBLE-473142-01 Preliminary Page 29 of 34CYBLE-473142-01PackagingThe CYBLE-473142-01 is offered in tape and reel packaging. Figure 13 details the tape dimensions used for the CYBLE-473142-01.Figure 13. CYBLE-473142-01 Tape Dimensions Figure 14 details the orientation of the CYBLE-473142-01 in the tape as well as the direction for unreeling.Figure 14. Component Orientation in Tape and Unreeling DirectionTable 20. Solder Reflow Peak TemperatureModule Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No. of CyclesCYBLE-473142-01 14-pad SMT 260 °C 30 seconds 2Table 21. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2Module Part Number Package MSL CYBLE-473142-01 14-pad SMT MSL 3

Document Number: CYBLE-473142-01 Preliminary Page 30 of 34CYBLE-473142-01Figure 15 details reel dimensions used for the CYBLE-473142-01.Figure 15. Reel DimensionsThe CYBLE-473142-01 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. Thecenter-of-mass for the CYBLE-473142-01 is detailed in Figure 16.Figure 16. CYBLE-473142-01 Center of Mass

Document Number: CYBLE-473142-01 Preliminary Page 31 of 34CYBLE-473142-01Ordering InformationTab le 22 lists the CYBLE-473142-01 part number and features. Table 22 also lists the target program for the respective moduleordering codes. Table 23 lists the reel shipment quantities for the CYBLE-473142-01.The CYBLE-473142-01 is offered in tape and reel packaging. The CYBLE-473142-01 ships in a reel size of 800 units. For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress salesrepresentative. To locate the nearest Cypress office, visit our website.Table 22. Ordering InformationOrdering Part NumberBase Part Number (Marking)CPU Speed (MHz)Flash Size (KB)RAM Size (KB)UART PWM Apple MFi Coprocessor Package Packaging ProgramCYBLE-473142-01 CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel A19WCP8745AT CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel FlexCCP8746AT CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel PlugCP8747AT CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel A60CeCP8748AT CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel FlexCeTable 23. Tape and Reel Package Quantity and Minimum Order AmountDescription Minimum Reel Quantity Maximum Reel Quantity CommentsReel Quantity 800 800 Ships in 800 unit reel quantities. Minimum Order Quantity (MOQ) 800 – –Order Increment (OI) 800 – –U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134U.S. Cypress Headquarter Contact Info (408) 943-2600Cypress website address http://www.cypress.com

Document Number: CYBLE-473142-01 Preliminary Page 32 of 34CYBLE-473142-01Acronyms Document ConventionsUnits of MeasureTable 24. Acronyms Used in this DocumentAcronym DescriptionBLE Bluetooth Low EnergyBluetooth SIG Bluetooth Special Interest GroupCE European ConformityCSA Canadian Standards AssociationEMI electromagnetic interferenceESD electrostatic dischargeFCC Federal Communications CommissionGPIO general-purpose input/outputISED Innovation, Science and Economic Devel-opment (Canada)IDE integrated design environmentKC Korea CertificationMIC Ministry of Internal Affairs and Communications (Japan)PCB printed circuit boardRX receiveQDID qualification design IDSMTsurface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBsTCPWM timer, counter, pulse width modulator (PWM)TUV Germany: Technischer Überwachungs-Verein (Technical Inspection Association)TX transmitTable 25. Units of MeasureSymbol Unit of Measure°C degree CelsiuskV kilovoltmA milliamperesmm millimetersmV millivoltμA microamperesμm micrometersMHz megahertzGHz gigahertzVvolt

Document Number: CYBLE-473142-01 Preliminary Page 33 of 34CYBLE-473142-01Document History Page Document Title: CYBLE-473142-01 EZ-BLE™ Module with HomeKitDocument Number: CYBLE-473142-01 PreliminaryRevision ECN Orig. of ChangeSubmission Date Description of ChangePRELIM DSO 12/26/2017 Datasheet for CYBLE-473142-01 module.

User manual_CYBLE-473142-01

Document Number: CYBLE-473142-01 Preliminary Page 2 of 34CYBLE-473142-01ContentsOverview............................................................................ 3Functional Block Diagram ........................................... 3Module Description...................................................... 3Pad Connection Interface ................................................ 5Recommended Host PCB Layout ................................... 6Module Connections ........................................................ 7Connections and Optional External Components ....... 7Power Connections (VDD) .......................................... 7External Reset (XRES)................................................ 8UART Connections...................................................... 8External Component Recommendation ...................... 8Critical Components List ........................................... 10Antenna Design......................................................... 10Bluetooth Baseband Core ............................................. 11Bluetooth Low Energy ............................................... 11Power Management Unit................................................ 12RF Power Management ............................................ 12Host Controller Power Management ......................... 12BBC Power Management.......................................... 12Microprocessor Unit....................................................... 13Floating Point Unit..................................................... 13On-Chip Flash ........................................................... 13OTP........................................................................... 13External Reset........................................................... 13Integrated Radio Transceiver ........................................ 14Transmitter Path........................................................ 14Digital Modulator ....................................................... 14Power Amplifier ......................................................... 14Receiver Path............................................................ 14Digital Demodulator and Bit Synchronizer................. 14Receiver Signal Strength Indicator............................ 14Calibration ................................................................. 15Internal LDO Regulator ............................................. 15Peripheral Transport Unit .............................................. 15UART Interface.......................................................... 15Peripheral UART Interface ........................................ 16ADC Port.......................................................................... 16PWM................................................................................. 16Triac Control ................................................................... 17Security Engine .............................................................. 17Electrical Characteristics............................................... 18Core Buck Regulator................................................. 19Digital LDO................................................................ 20RF LDO ..................................................................... 21Digital I/O Characteristics.......................................... 22Current Consumption ................................................ 22RF Specifications ........................................................... 23Timing and AC Characteristics ..................................... 24UART Timing............................................................. 24Environmental Specifications ....................................... 25Environmental Compliance ....................................... 25RF Certification.......................................................... 25Safety Certification .................................................... 25Environmental Conditions ......................................... 25ESD and EMI Protection ........................................... 25Regulatory Information.................................................. 26FCC........................................................................... 26Innovation, Science and Economic Development (ISED) Canada Certification......................................................... 27European Declaration of Conformity ......................... 28Packaging........................................................................ 29Ordering Information...................................................... 31Acronyms........................................................................ 32Document Conventions ................................................. 32Units of Measure ....................................................... 32Document History Page................................................. 33Sales, Solutions, and Legal Information ...................... 34Worldwide Sales and Design Support....................... 34Products .................................................................... 34PSoC® Solutions ...................................................... 34Cypress Developer Community................................. 34Technical Support ..................................................... 34

Document Number: CYBLE-473142-01 Preliminary Page 3 of 34CYBLE-473142-01OverviewFunctional Block DiagramFigure 1 illustrates the CYBLE-473142-01 functional block diagram.Figure 1. Functional Block DiagramModule DescriptionThe CYBLE-473142-01 module is a complete module designed to be soldered to the applications main board. Module Dimensions and DrawingCypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selectionswill still guarantee that all mechanical specifications and module certifications are maintained. Any changes to the current BOM forthe CYBLE-473142-01 will not be made until approval is provided by the end customer for this product. The CYBLE-473142-01 willbe held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 4. All dimensions are in millimeters (mm).Table 1. Module Design DimensionsSee Figure 2 for the mechanical reference drawing for CYBLE-473142-01.Dimension Item SpecificationModule dimensions Length (X) 14.70 ± 0.15 mmWidth (Y) 20.00 ± 0.15 mmAntenna location dimensions Length (X) 14.70 mmWidth (Y) 4.80 mmPCB thickness Height (H) 0.80 ± 0.10 mmShield height Height (H) 1.80 mmMaximum component height Height (H) 0.60 mm typicalTotal module thickness (bottom of module to highest component) Height (H) 2.60 mm typical

Document Number: CYBLE-473142-01 Preliminary Page 4 of 34CYBLE-473142-01Figure 2. Module Mechanical DrawingBottom View (Seen from Bottom)Side ViewTop View (See from Top)Notes4. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see “Recommended Host PCB Layout” on page 6.5. The CYBLE-473142-01 includes castellated pad connections, denoted as the circular openings at the pad location above.

Document Number: CYBLE-473142-01 Preliminary Page 5 of 34CYBLE-473142-01Pad Connection InterfaceAs shown in the bottom view of Figure 2 on page 4, the CYBLE-473142-01 has seven main connections that are connected to thehost board via castellated solder pads (“CSP”). The CYBLE-473142-01 also includes additional solder pad connections (“SP”) usedfor debug or testing on the bottom side of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensionsof the CYBLE-473142-01 module. Figure 3. Solder Pad Dimensions (Seen from Bottom)To maximize RF performance, the host layout should follow these recommendations:1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 4) mustcontain no ground or signal traces. This keep out area requirement applies to all layers of the host board. 2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB traceantenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Pleaserefer to AN96841 for module placement best practices.3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module PCB trace antennamay contain an additional keep out area, where no grounding or signal traces are contained. The keep out area applies to all layersof the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBLE-473142-01 PCB Trace AntennaTable 2. Connection DescriptionName Connections Connection Type Pad Length Dimension Pad Width Dimension Pad PitchCSP 7 Castellated Solder Pads 2.00 mm 1.30 mm 2.00 mmSP 7 Solder Pads 0.65 mm (Radius) 0.65 mm (Radius) N/ACastellated Solder Pad (CSP) and Solder Pad (SP) Connection (Seen from Bottom)Optional Host PCB Keep Out Area Around Chip Antenna

Document Number: CYBLE-473142-01 Preliminary Page 6 of 34CYBLE-473142-01Recommended Host PCB LayoutFigure 5 (Dimensioned) and Figure 6 (Relative to Origin) provide the recommended host PCB layout pattern for theCYBLE-473142-01. Pad length of 1.27 mm (0.655 mm from center of the pad on either side) shown in Figure 6 is the minimumrecommended host pad length. All dimensions are in millimeters. Figure 5. CYBLE-473142-01 Host Layout (Dimensioned) Figure 6. CYBLE-473142-01 Host Layout (Relative to Origin)Top View (Seen on Host PCB)Top View (Seen on Host PCB)

Document Number: CYBLE-473142-01 Preliminary Page 7 of 34CYBLE-473142-01Module ConnectionsTab le 3 details the solder pad connection definitions and available functions for each connection pad. Table 3 lists the solder pads onthe CYBLE-473142-01, the silicon device pin, and denotes what functions are available for each solder pad. Table 3 also lists theprimary/intended function for each solder pad for the application this module was specifically designed for.Connections and Optional External ComponentsPower Connections (VDD)The CYBLE-473142-01 contains one power supply connection, VDD.VDD accepts a supply input of 3.30 V. Tabl e 9 provides this specification. The maximum power supply ripple for this power connectionis 300 mV, as shown in Table 9. Considerations and Optional Components for Brown Out (BO)ConditionsPower supply design must be completed to ensure that the CYBLE-473142-01 module does not encounter a Brown Out condition,which can lead to unexpected funcitonality, or module lock up. A Brown Out condition may be met if power supply provided to themodule during power up or reset is in the range shown below: VIL ≤ VDD ≤ VIHRefer to Table 13 for the VIL and VIH specifications. System design should ensure that the condition above is not encountered when power is removed from the system. In the event thatthis cannot be guaranteed (i.e. battery installation, high value power capacitors with slow discharge), it is recommended that anexternal voltage detection device be used to prevent the Brown Out voltage range from occuring during power removal. Please referto Figure 7 for the recommended circuit design when using an external voltage detection IC.Table 3. Solder Pad Connection Definitions Pad Num-ber Pad Name UART PWM GPIO Primary Function1 VDD Power Supply Input (3.30 V) Power Supply Input2 GND Ground Connection Ground Connection3PWM1 33PWM R, G, B, or W Function4PWM2 33PWM R, G, B, or W Function5PWM3 33PWM R, G, B, or W Function6PWM4 33PWM R, G, B, or W Function7ADC ADC Input8PUART_TX 3(PUART_TXD) Peripheral UART TXD9PUART_RX 3(PUART_RXD) 33Peripheral UART RXD10 XRES External Reset Hardware Connection Input External Reset (Active Low)11 UART_RXD 3(UART_RXD) UART RXD12 UART_TXD 3(UART_TXD) UART TXD13 UART_CTS 3(UART_CTS) UART CTS14 UART_RTS 3(UART_RTS) UART RTSGND GND Ground Connection Ground ConnectionsMust be soldered to host boardGND GND Ground Connection

Document Number: CYBLE-473142-01 Preliminary Page 8 of 34CYBLE-473142-01Figure 7. Reference Circuit Block Diagram for External Voltage Detection ICIn the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling themodule will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potential cause issuesthat cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition. External Reset (XRES)The CYBLE-473142-01 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. Thisaction can also be envoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal,which is an input to the CYBLE-473142-01 module (solder pad 3). The CYBLE-473142-01 module does not require an external pull-upresistor on the XRES input During power on operation, the XRES connection to the CYBLE-473142-01 is required to be held low 50 ms after the VDD powersupply input to the module is stable. This can be accomplished in the following ways: nThe host device should connect a GPIO to the XRES of Cypress CYBLE-473142-01 module and pull XRES low until VDD is stable.XRES is recommended to be released 50 ms after VDD is stable.nIf the XRES connection of the CYBLE-473142-01 module is not used in the application, a 0.33 uF capacitor may be connected tothe XRES solder pad of the CYBLE-473142-01 in order to delay the XRES release. The capacitor value for this recommendedimplementation is approximate, and the exact value may differ depending on the VDD power supply ramp time of the system. Thecapacitor value should result in an XRES release timing of 50 ms after VDD stability. nThe XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable.Refer to Figure 10 on page 14 for XRES operating and timing requirements during power on events.UART ConnectionsFor full UART functionality, all UART signals must be connected to the Host device. If full UART functionality is not being used, andonly UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS andCTS: nUART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on. nUART CTS: Must by pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to themodule. External Component RecommendationPower Supply CircuitryIt is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite beadbetween the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positionedas close as possible to the module pin connection. If used, the recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).Apple MFi Authentication Coprocessor InterfaceThe CYBLE-473142-01 comes with an integrated MFi authentication co-processor. No additoinal connections are required to be madeto the module to enable Apple HomeKit functionality. All connections required are internally routed on the module PCB.

Document Number: CYBLE-473142-01 Preliminary Page 9 of 34CYBLE-473142-01Figure 8 illustrates the CYBLE-473142-01 schematic.Figure 8. CYBLE-473142-01 Schematic Diagram

Document Number: CYBLE-473142-01 Preliminary Page 10 of 34CYBLE-473142-01Critical Components ListTab le 4 details the critical components used in the CYBLE-473142-01 module.Table 4. Critical Component ListAntenna DesignTab le 5 details the PCB trace antenna used in the CYBLE-473142-01 module. Table 5. Trace Antenna SpecificationsComponent Reference Designator DescriptionAuthentication Co-Processor U1 Apple Authentication Co-processorSilicon U2 40-pin QFN BLE Silicon Device - CYW20719 B1 SiliconPA/LNA U3 17-pin QFN - Skyworks RFX2401CCrystal Y1 24.000 MHz, 12PFItem DescriptionFrequency Range 2402 – 2480 MHzPeak Gain –0.5 dBi maximum

Document Number: CYBLE-473142-01 Preliminary Page 11 of 34CYBLE-473142-01Bluetooth Baseband CoreThe Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,handles data flow control, schedules TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data intobaseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, itindependently handles host controller interface (HCI) event types, and HCI command types.The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of theTX/RX data before sending over the air:nSymbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),data decryption, and data dewhitening in the receiver.nData framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in thetransmitter.Bluetooth Low EnergyThe CYBLE-473142-01 supports single-mode Bluetooth LE operation. The CYBLE-473142-01 supports all Bluetooth 4.2 and legacyLE features, with the following benefits: nLE data packet length extensionnLE secure connections nLink layer privacynEnables Bluetooth Smart sensors to access the Internet directly via IPv6/6LoWPANLink Control LayerThe link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).This layer consists of the command controller that takes commands from the software, and other controllers that are activated orconfigured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth® LinkController. nMajor states: pStandby pConnection

Document Number: CYBLE-473142-01 Preliminary Page 12 of 34CYBLE-473142-01Power Management UnitThe Power Management Unit (PMU) provides power management features that can be invoked through power management registersor packet handling in the baseband core. This section contains descriptions of the PMU features.Figure 9. Power Management Unit of CYW20719RF Power ManagementFigure 9 shows the CYBLE-473142-01 power management unit (PMU) block diagram that is contained in the CYW20719 silicondevice. The CYW20719 includes an integrated buck regulator, a bypass LDO, a capless LDO, and an additional 1.2 V LDO for RF.Host Controller Power ManagementPower is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls thedisabling of the on-chip regulator when in HIDOFF (deep sleep) mode.BBC Power ManagementThere are several low-power operations for the BBC:nPhysical layer packet handling turns RF on and off dynamically within packet TX and RX.nBluetooth-specified low-power connection mode. While in these low-power connection modes, the CYBLE-473142-01 runs on theLow Power Oscillator and wakes up after a predefined time period.The CYBLE-473142-01 automatically adjusts its power dissipation based on user activity. It supports the following power modes:nActive modenIdle modenSleep mode (not enabled for the specific application the CYBLE-473142-01 is used in)nHIDOFF (deep sleep) mode The CYBLE-473142-01 transitions to the next lower state after a programmable period of user inactivity. When user activityresumes, the CYBLE-473142-01 immediately enters Active mode.In HIDOFF mode, the CYBLE-473142-01 baseband and core are powered off by disabling power to VDDC_OUT and PAVDD. TheVDDO domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chippower consumption and is used for extended periods of inactivity.

Document Number: CYBLE-473142-01 Preliminary Page 13 of 34CYBLE-473142-01Microprocessor UnitThe CYBLE-473142-01 microprocessor unit runs software from the link control (LC) layer up to the host controller interface (HCI).The microprocessor is a Cortex®-M4 32-bit RISC processor with embedded ICE-RT debug and serial wire debug (SWD) interfaceunits. The microprocessor also includes 2 MB of ROM memory for program storage and 512 KB of RAM for data scratch-pad.The internal ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. Atpower-up, the lower layer protocol stack is executed from the internal ROM.External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. The devicealso supports the integration of user applications and profiles. Patches and applications can be stored in on-chip flash.Floating Point UnitThe CYBLE-473142-01 includes the CM4 single precision IEEE-754 compliant floating point unit. For additional details, see the Cor-tex-M4 manual.On-Chip FlashThe silicon device used in the CYBLE-473142-01 module includes 1 MB of on-chip flash. This flash can be used for direct programexecution or for non-volatile data. Typical usage for the on-chip flash includes:nChip configurationnPatchesnPeer addresses and link keysnApplication codenApplication non-volatile datanProduct informationOTPThe CYBLE-473142-01 includes 2 KB of one-time programmable (OTP) memory. This memory can be used by the factory to storeproduct specific information. Note: Use of OTP requires a 3 V supply to be present at all times.External ResetAn external active-low reset signal, XRES, can be used to put the CYBLE-473142-01 in the reset state. An external voltage detectorreset IC with 50 ms delay is needed on the XRES. The XRES should be released only after the VDDO supply voltage level has beenstabilized for 50 ms.

Document Number: CYBLE-473142-01 Preliminary Page 14 of 34CYBLE-473142-01Figure 10. Reset TimingIntegrated Radio TransceiverThe CYBLE-473142-01 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth wireless systems. It has beendesigned to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unli-censed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the requirements to provide thehighest communication link quality of service.Transmitter PathThe CYBLE-473142-01 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISMband.Digital ModulatorThe digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizesany frequency drift or anomalies in the modulation characteristics of the transmitted signal.Power AmplifierThe CYBLE-473142-01 has an integrated power amplifier (PA) on the silicon device as well as a high power external power amplifier(PA) integrated on the module. The total output power that this module is designed to achieve is +8 dBm.Receiver PathThe receiver path uses a low IF scheme to down convert the received signal for demodulation in the digital demodulator and bit syn-chronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in thenoisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBLE-473142-01 to beused in most applications without off-chip filtering.Digital Demodulator and Bit SynchronizerThe digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit syn-chronization algorithm.Receiver Signal Strength IndicatorThe radio portion of the CYBLE-473142-01 provides a receiver signal strength indicator (RSSI) to the baseband. This enables thecontroller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determinewhether the transmitter should increase or decrease its output power.

Document Number: CYBLE-473142-01 Preliminary Page 15 of 34CYBLE-473142-01CalibrationThe CYBLE-473142-01 radio transceiver features a self-contained automated calibration scheme. No user interaction is requiredduring normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching net-work, and amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes processand temperature variations into account, and it takes place transparently during normal operation and hop setting times.Internal LDO RegulatorThe CYBLE-473142-01 has an integrated 1.2 V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO reg-ulator operates from a 1.425 V to 3.63 V input supply with a 30 mA maximum load current.Peripheral Transport UnitUART InterfaceThe CYBLE-473142-01 includes a UART interface for factory programming as well as when operating as a BT HCI device in a sys-tem with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baudrates from 9600 bps to 6 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via avendor-specific UART HCI command. The CYBLE-473142-01 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to sup-port enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2kbaud.The UART clock default setting is 24 MHz. The baud rate of the CYBLE-473142-01 UART is controlled by two values. The first is aUART clock divisor (set in the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rateadjustment (set in the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of eachbit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can beinserted into the end of each bit time. Table 6 contains example values to generate common baud rates with a 24 MHz UART clock.Tab le 7 contains example values to generate common baud rates with a 48 MHz UART clock.Table 6. Common Baud Rate Examples, 24 MHz ClockBaud Rate (bps) DHBR DLBR Mode Error (%)3M 0xFF 0xF8 High rate 0.002M 0XFF 0XF4 High rate 0.001.5M 0X00 0XFF Normal 0.001M 0x44 0xFF Normal 0.00921600 0x55 0xFF Normal 0.16460800 0x22 0xFD Normal 0.16230400 0x44 0xFA Normal 0.16115200 0x00 0xF3 Normal 0.1638400 0x01 0xD9 Normal 0.00Table 7. Common Baud Rate Examples, 48 MHz ClockBaud Rate (bps) High Rate Low Rate Mode Error (%)6M 0xFF 0xF8 High rate 0.004M 0xFF 0xF4 High rate 0.003M 0x0 0xFF Normal 0.002M 0x44 0xFF Normal 0.001.5M 0x00 0xFE Normal 0.001M 0x00 0xFD Normal 0.00921600 0x22 0xFD Normal 0.16460800 0x44 0xFA Normal 0.16

Document Number: CYBLE-473142-01 Preliminary Page 16 of 34CYBLE-473142-01Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allowsthe host to adjust the contents of the baud rate registers.The CYBLE-473142-01 UART operates correctly with the host UART as long as the combined baud rate error of the two devices iswithin ±5%.Peripheral UART InterfaceThe CYBLE-473142-01 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed throughthe optional I/O ports, which can be configured individually and separately for each functional pin. ADC PortThe ADC block is a single switched-cap Σ-Δ ADC core for audio and DC measurement. It operates at the 12 MHz clock rate. Theinternal bandgap reference has ±5% accuracy without calibration. Different calibration and digital correction schemes can be appliedto reduce ADC absolute error and improve measurement accuracy in DC mode.PWMThe CYBLE-473142-01 has five PWMs. The PWM module consists of the following:nPWM1–5. Each of the five PWM channels contains the following registers:p16-bit initial value register (read/write)p16-bit toggle register (read/write)p16-bit PWM counter value register (read)nPWM configuration register shared among PWM1–5 (read/write). This 18-bit register is used:pTo configure each PWM channelpTo select the clock of each PWM channel pTo change the phase of each PWM channelFigure 11 shows the structure of one PWM.230400 0x0 0xF3 Normal 0.16115200 0x1 0xE6 Normal –0.0857600 0x1 0xCC Normal 0.0438400 0x11 0xB2 Normal 0.0019200 0x22 0x64 Normal 0.00Table 7. Common Baud Rate Examples, 48 MHz Clock (continued)Baud Rate (bps) High Rate Low Rate Mode Error (%)

Document Number: CYBLE-473142-01 Preliminary Page 17 of 34CYBLE-473142-01Figure 11. PWM Block DiagramTriac ControlThe CYBLE-473142-01 includes hardware support for zero-crossing detection and trigger control for up to four triacs. TheCYBLE-473142-01 detects zero-crossing on the AC zero detection line and uses that to provide a pulse that is offset from the zerocrossing. This allows the CYBLE-473142-01 to be used in dimmer applications, as well as any other applications that require a con-trol signal that is offset from an input event.The zero-crossing hardware includes an option to suppress glitches.Security EngineThe CYBLE-473142-01 includes a hardware security accelerator which greatly decreases the time required to perform typical secu-rity operations. Access to the hardware block is provided via a firmware interface (see firmware documentation for details).Thiesecurity engine includes:nPublic key acceleration (PKA) cryptographynAES-CTR/CBC-MAC/CCM accelerationnSHA2 message hash and HMAC accelerationnRSA encryption and decryption of modulus sizes up to 2048 bitsnElliptic curve Diffie-Hellman in prime field GF(p)nGeneric modular math functions

Document Number: CYBLE-473142-01 Preliminary Page 18 of 34CYBLE-473142-01Electrical CharacteristicsNote: All voltages listed in Table 8 are referenced to VDD.Tab le 9 shows the power supply characteristics for the range TJ = 0°C to 125°C.Table 8. Absolute Maximum VoltagesRequirement ParameterSpecificationUnitMinimum Nominal MaximumAmbient Temperature of Operation –30 25 105 °CStorage temperature –30 – 110 °CESD Tolerance HBM (Silicon) –2000 – 2000 VESD Tolerance MM (Silicon) –100 – 100 VESD Tolerance CDM (Silicon) –500 – 500 VLatch-up (Silicon) – 200 – mATable 9. Power Supply SpecificationsParameter Conditions Min. Typical Max. UnitVDD input Module Input 3.0 3.3 3.6 VVDD Ripple Module Input – – 100 mVVBAT Input Internal to Module (not accessible) 1.62 3.3 3.6 VPMU turn-on time VBAT is ready. – – 300 μs

Document Number: CYBLE-473142-01 Preliminary Page 19 of 34CYBLE-473142-01Core Buck RegulatornMinimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature,and aging.nMaximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes anydecoupling capacitors connected at the load side, if any.Table 10. Core Buck Regulator (Internal to Module)Parameter Conditions Min. Typ. Max. UnitInput supply voltage DC, VBAT DC voltage range inclusive of disturbances 2.1 3.3 3.63 VCBUCK output current LPOM only – – 65 mAOutput over-current limit Peak inductor current TBD – – mAOutput voltage range Programmable, 30mV/stepdefault = 1.2V (bits=0000)1.2 1.2 1.5 VOutput voltage DC accuracy Includes load and line regulation:• Before trimming• After trimming–4–2–+4+2%%LPOM ripple voltage, static Measured with 20 MHz bandwidth limit, static load. Max ripple based on VBAT=3V, Vout=1.2VInductor:0806 inch-size, Tmax=1 mm, 2.2 μH ±25%, DCR=114 mW ±20%, ACR<1W (for frequency <1 MHz)Capacitor:1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor + board total-ESR < 20 mW– – 30 mVppLPOM efficiency (high load) 10–50 mA load current, Vout=1.2V, Vbat=3V @25°CInductor:0806 inch-size, Tmax=1 mm,2.2 μH ±25%, DCR=114 mW ±20%, ACR<1W (for frequency<1 MHz)Capacitor:1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor +board total-ESR < 20 mW–85–%LPOM efficiency (low load) 1–5 mA load current, Vout=1.2V, Vbat=3V @25°CInductor:0806 inch-size, Tmax=1 mm,2.2 μH ±25%, DCR=114 mW ±20%, ACR<1W (for frequency<1 MHz)Capacitor:1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor +board total-ESR < 20 mW–80–%Startup time see Table 11 on page 20.––––External inductor L 2.2 μH ±25%, DCR=114 mW ±20%, ACR<1W (for frequency<1 MHz)–2.2–μHExternal output capacitor, Cout 1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC capacitor +board total-ESR < 20 mW0.7 1 1.1 μFExternal input capacitor, Cin For SR_VDDBAT pinCeramic, X5R, 0402, ESR<30 mW at 4 MHz, +/-20%, 6.3V, 4.7 μF0.7 4.7 5.64 μFInput supply voltage ramp-up time 0 to 3.3V 40 – – μs

Document Number: CYBLE-473142-01 Preliminary Page 20 of 34CYBLE-473142-01Digital LDOTable 11. Digital LDO (Internal to Module)Parameter Conditions Min. Typ. Max. UnitInput supply voltage, Vin Minimum Vin=Vo+0.12V requirement must be met under maximum load. 1.2 1.2 1.6 VNominal output voltage,Vo Internal default bit setting – 1.1 – VOutput voltage programmability RangeStep sizeAccuracy at any step (including line/load regulation) before trimmingAccuracy at any step (including line/load regulation) after trimming0.9––4–2–10––1.25–+4+2VmV%%Dropout voltage At maximum load – – 120 mVOutput current DC load 0.211. By default, an internal loading of ~0.2 mA resides inside the LDO. This is to ensure the LDO is stable with zero loading from the core. After the core is up, digital logic can disable this internal loading by setting i_ldo_cntl<8:7> to 00.–40mAOutput loading capacitor Internal, including the decoupling capacitor to be placed next to the load and the equivalent loading capacitor by the core.4–10nFQuiescent current At no load, excluding main bandgap Iq – 90 120 μALine regulation Vin from (Vo+0.12V) to 1.5V; 40 mA load – – 5 mV/VLoad regulation Load from 1 mA to 25 mA; Vin (Vo+0.12V) – 0.025 0.045 mV/mALeakage current In full power-down mode or bypass mode:• Junction temperature: 25°C• Junction temperature: 125°C––0.051.10.25.0μAμAPSRR @1 kHz, Vin, Vo+0.12VOutput cap of 4 nF~10 nF40 – – dBPMU startup time VBAT is up and steady. Time from HID_OFF falling edge to DIGLDO reaching 99% of Vo. – 100 – μsLDO turn-on time LDO turn-on time when balance of chip is up – – 22 μsExternal input capacitor Only use an external input capacitor at VDD_DIGLDO pin if it is not supplied from CBUCK output. –12.2μF

Document Number: CYBLE-473142-01 Preliminary Page 21 of 34CYBLE-473142-01RF LDOTable 12. RF LDO (Internal to Module)Parameter Conditions Min. Typ. Max. UnitInput supply voltage, Vin Min Vin=Vo+0.15V = 1.35V (for Vo=1.2V)Dropout voltage requirement must be met under maximum load.1.2 1.35 1.5 VNominal output voltage,Vo Internal default bit setting 000 – 1.2 – VOutput voltage programmability RangeStep sizeAccuracy at any step (including line/load regulation) Accuracy at any step (including line/load regulation) after trimming1.1––4–2–25––1.275–+4+2VmV%%Dropout voltage At maximum load – – 150 mVOutput current TBD 0.1 – 25 mAQuiescent current No load – 44 – μALine regulation Vin from (Vo+0.15V) to 1.5V; 25 mA load – – 5.5 mV/VLoad regulation Load from 1 mA to 25 mA; Vin ≥ (Vo+0.15V) – 0.025 0.045 mV/mALoad step error Load step from 1 mA–25 mA in 1 μs and 25 mA–1 mA in 1μs; Vin(Vo+0.15V); Co=2.2 μF––35mVLeakage current Power-down junction temperature: 85°C – – 10 μAOutput noise @30 kHz, 25 mA load, Co= 2.2 μF @100 kHz, 25 mA load, Co= 2.2 μF––6035nV/√HznV/√HzPSRR @1kHz, Input > 1.35V, Co= 2.2 μF, Vo=1.2V 20 – – dBLDO turn-on time LDO turn-on time when balance of chip is up – 140 180 μsIn-rush current Vin=Vo+0.15V to 1.5V, Co=2.2 μF, no load – – 100 mAExternal output capacitor, Co Total ESR (trace/cap): 5 m–240 mW 0.5 2.2 4.7 μFExternal input capacitor Only use an external input capacitor at VDD_DIGLDO pin if it is not supplied from CBUCK output. –12.2μFNote: Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.

Document Number: CYBLE-473142-01 Preliminary Page 22 of 34CYBLE-473142-01Digital I/O CharacteristicsCurrent ConsumptionIn Table 14, current consumption measurements are taken at VBAT with the assumption that VBAT is connected to VDDIO andLDOIN. Module current consumption measurements are taken at VDD.Table 13. Digital I/O CharacteristicsCharacteristics Symbol Minimum Typical Maximum UnitInput low voltage (VDD = 3.3V) VIL ––0.8VInput high voltage (VDD = 3.3V) VIH 2.0 – – VOutput low voltage VOL ––0.4VOutput high voltage VOH VDD – 0.4V – – VInput low current IIL ––1.0μAInput high current IIH ––1.0μAOutput low current (VDD = 3.3V, VOL = 0.4V) IOL ––2.0mAOutput high current (VDD = 3.3V, VOH = 2.9V) IOH ––4.0mAInput capacitance CIN ––0.4pFTable 14. BLE Current ConsumptionProduct Operational Mode Conditions Typical UnitCYW20719 B1(Silicon)Receiving Receiver and baseband are both operating, 100% ON, silicon only. 5.8 mATransmitting Transmitter and baseband are both operating, 100% ON, silicon only. 5.7 mAPDS 512 KB SRAM memory retention, silicon only. 70 μADeep Sleep 16 KB SRAM memory retention, silicon only. 1 μAHIDOFF Wakeup only from XRES. No SRAM memory retention, silicon only.350 nAConnection, 1-s Avg. Average Power, 1-second connection interval, silicon only. Deep Sleep mode enabled during non-TX/RX17 μAConnection, 4-s Avg. Average Power, 4-second connection interval, silicon only. Deep Sleep mode enabled during non-TX/RX5μACYBLE-473142-01 (Module)Receiving Receiver and baseband are both operating, 100% ON, module. 13.3 mATransmitting Transmitter and baseband are both operating, 100% ON, module. 32.7 mAConnection Average Power, using FW V0.3.6 of actual application 9.0 mAAdvertising Average Power, using FW V0.3.6 of actual application 11.0mA

Document Number: CYBLE-473142-01 Preliminary Page 23 of 34CYBLE-473142-01RF SpecificationsNote: Table 15 and Table 16 apply to single-ended industrial temperatures. Unused inputs are left open.Table 15. Receiver RF SpecificationsParameter Mode and Conditions Min Typ Max UnitReceiver SectionFrequency range – 2402 – 2480 MHzRX sensitivity GFSK, BDR GFSK 0.1% BER, 1 MbpsModule– –93.0 – dBmMaximum input – –20 – – dBmTable 16. Transmitter RF SpecificationsParameter Min Typ Max UnitTransmitter SectionFrequency range 2402 – 2480 MHzClass 2: GFSK Tx power (silicon) – 4 – dBmClass 2: GFSK Tx power (module) – 8 – dBm20 dB bandwidth – 930 1000 kHzFrequency DriftDH1 packet –25 – +25 kHzDH3 packet –40 – +40 kHzDH5 packet –40 – +40 kHzDrift rate –20 20 kHz/50 µsFrequency DeviationAverage deviation in payload(sequence used is 00001111)140 – 175 kHzMaximum deviation in payload(sequence used is 10101010)115 – – kHzChannel spacing – 1 – MHzTable 17. BLE RF SpecificationsParameter Conditions Minimum Typical Maximum UnitFrequency range N/A 2402 – 2480 MHzRx sensitivity11. Dirty Tx is Off.GFSK, BDR GFSK 0.1% BER 0.1% BER, 1 Mbps – –93.0 – dBmTx power N/A – 4 – dBmMod Char: Delta F1 average N/A 225 255 275 kHzMod Char: Delta F2 max22. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.N/A 99.9 – – %Mod Char: Ratio N/A 0.8 0.95 – %

Document Number: CYBLE-473142-01 Preliminary Page 24 of 34CYBLE-473142-01Timing and AC CharacteristicsIn this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.UART TimingFigure 12. UART TimingTable 18. UART Timing SpecificationsReference Characteristics Min. Typ. Max. Unit1 Delay time, UART_CTS_N low to UART_TXD valid. – – 1.50 Bit periods2 Setup time, UART_CTS_N high before midpoint of stop bit. – – 0.67 Bit periods3 Delay time, midpoint of stop bit to UART_RTS_N high. – – 1.33 Bit periods

Document Number: CYBLE-473142-01 Preliminary Page 25 of 34CYBLE-473142-01Environmental SpecificationsEnvironmental ComplianceThis Cypress BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS), Halogen-Free (HF), andREACH directives. The Cypress module and components used to produce this module are RoHS, HF, and REACH compliant.RF CertificationThe CYBLE-473142-01 module is certified under the following RF certification standards:nFCC: WAP3136nISED: 7922A-3136nCESafety CertificationThe CYBLE-473142-01 module complies with the following safety regulations:nUnderwriters Laboratories, Inc. (UL): Filing E331901nCSAnTUVEnvironmental ConditionsTab le 19 describes the operating and storage conditions for the Cypress BLE module.ESD and EMI ProtectionExposed components require special attention to ESD and electromagnetic interference (EMI).A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosurenear the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.Table 19. Environmental Conditions for CYBLE-473142-01Description Minimum Specification Maximum SpecificationOperating temperature −30 °C 105 °COperating humidity (relative, non-condensation) 5% 85%Thermal ramp rate – 10 °C/minuteStorage temperature –40 °C 110 °CStorage temperature and humidity – 110 °C at 85%ESD: Module integrated into system Components[6] –15 kV Air2.0 kV ContactNote6. This does not apply to the RF pins (ANT).

Document Number: CYBLE-473142-01 Preliminary Page 26 of 34CYBLE-473142-01Regulatory InformationFCCFCC NOTICE:The device CYBLE-473142-01 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitterapproval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This devicemay not cause harmful interference, and (2) This device must accept any interference received, including interference that may causeundesired operation.CAUTION:The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved byCypress Semiconductor may void the user's authority to operate the equipment.This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipmentgenerates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may causeharmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipmentoff and on, the user is encouraged to try to correct the interference by one or more of the following measures:nReorient or relocate the receiving antenna. nIncrease the separation between the equipment and receiver. nConnect the equipment into an outlet on a circuit different from that to which the receiver is connected. nConsult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visiblelabel on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as wellas the FCC Notice above. The FCC identifier is FCC ID: WAP3136.In any case the end product must be labeled exterior with “Contains FCC ID: WAP3136”.ANTENNA WARNING: This device is tested with a standard SMA connector and with the antenna listed in Table 5 on page 10. When integrated in the OEMsproduct, this fixed antenna requires installation preventing end-users from replacing them with non-approved antennas. Any antennanot in Table 5 on page 10 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 foremissions.RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approvedantenna in the previous.The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennasin Table 5 on page 10, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removalinstructions about the integrated radio module is not allowed.The radiated output power of CYBLE-473142-01 with the integrated PCB trace antenna (FCC ID: WAP3136) is far below the FCCradio frequency exposure limits. Nevertheless, use CYBLE-473142-01 in such a manner that minimizes the potential for humancontact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided withtransmitter operating conditions for satisfying RF exposure compliance.

Document Number: CYBLE-473142-01 Preliminary Page 27 of 34CYBLE-473142-01Innovation, Science and Economic Development(ISED) Canada CertificationCYBLE-473142-01 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED)Canada. License: IC: 7922A-3136Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensurecompliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance fromwww.ic.gc.ca.This device has been designed to operate with the antennas listed in Table 5 on page 10, having a maximum gain of -0.5 dBi. Antennasnot included in Table 5 on page 10 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The requiredantenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with anyother antenna or transmitter.ISED NOTICE:The device CYBLE-473142-01 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets therequirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) Thisdevice may not cause harmful interference, and (2) This device must accept any interference received, including interference thatmay cause undesired operation.L'appareil CYBLE-473142-01, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond auxexigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditionssuivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, ycompris les interférences pouvant entraîner un fonctionnement indésirable.ISED INTERFERENCE STATEMENT FOR CANADAThis device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s).Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept anyinterference, including interference that may cause undesired operation of the device.Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte delicence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateurde l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonction-nement.ISED RADIATION EXPOSURE STATEMENT FOR CANADAThis equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should beinstalled and operated with a minimum distance 15mm between the radiator and the operator. Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé. Cet équipementdoit être installé et utilisé avec une distance minimale de 15 mm entre le radiateur et l'opérateur.LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visiblelabel on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well asthe ISED Notice above. The IC identifier is 7922A-3136. In any case, the end product must be labeled in its exterior with "ContainsIC: 7922A-3136".Le fabricant d'équipement d'origine (OEM) doit s'assurer que les exigences d'étiquetage ISED sont respectées. Cela comprend uneétiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Cypress Semiconductor IC approprié pour ce produitainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-3136. En tout cas, le produit final doit être étiqueté dans son extérieuravec "Contient IC: 7922A-3136".

Document Number: CYBLE-473142-01 Preliminary Page 28 of 34CYBLE-473142-01European Declaration of ConformityHereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-473142-01 complies with the essential requirements andother relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive2014, the end-customer equipment should be labeled as follows:All versions of the CYBLE-473142-01 in the specified reference design can be used in the following countries: Austria, Belgium,Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

Document Number: CYBLE-473142-01 Preliminary Page 29 of 34CYBLE-473142-01PackagingThe CYBLE-473142-01 is offered in tape and reel packaging. Figure 13 details the tape dimensions used for the CYBLE-473142-01.Figure 13. CYBLE-473142-01 Tape Dimensions Figure 14 details the orientation of the CYBLE-473142-01 in the tape as well as the direction for unreeling.Figure 14. Component Orientation in Tape and Unreeling DirectionTable 20. Solder Reflow Peak TemperatureModule Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No. of CyclesCYBLE-473142-01 14-pad SMT 260 °C 30 seconds 2Table 21. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2Module Part Number Package MSL CYBLE-473142-01 14-pad SMT MSL 3

Document Number: CYBLE-473142-01 Preliminary Page 30 of 34CYBLE-473142-01Figure 15 details reel dimensions used for the CYBLE-473142-01.Figure 15. Reel DimensionsThe CYBLE-473142-01 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. Thecenter-of-mass for the CYBLE-473142-01 is detailed in Figure 16.Figure 16. CYBLE-473142-01 Center of Mass

Document Number: CYBLE-473142-01 Preliminary Page 31 of 34CYBLE-473142-01Ordering InformationTab le 22 lists the CYBLE-473142-01 part number and features. Table 22 also lists the target program for the respective moduleordering codes. Table 23 lists the reel shipment quantities for the CYBLE-473142-01.The CYBLE-473142-01 is offered in tape and reel packaging. The CYBLE-473142-01 ships in a reel size of 800 units. For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress salesrepresentative. To locate the nearest Cypress office, visit our website.Table 22. Ordering InformationOrdering Part NumberBase Part Number (Marking)CPU Speed (MHz)Flash Size (KB)RAM Size (KB)UART PWM Apple MFi Coprocessor Package Packaging ProgramCYBLE-473142-01 CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel A19WCP8745AT CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel FlexCCP8746AT CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel PlugCP8747AT CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel A60CeCP8748AT CYBLE-473142-01 24 1024 512 Yes 5 Yes 14-SMT Tape and Reel FlexCeTable 23. Tape and Reel Package Quantity and Minimum Order AmountDescription Minimum Reel Quantity Maximum Reel Quantity CommentsReel Quantity 800 800 Ships in 800 unit reel quantities. Minimum Order Quantity (MOQ) 800 – –Order Increment (OI) 800 – –U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134U.S. Cypress Headquarter Contact Info (408) 943-2600Cypress website address http://www.cypress.com

Document Number: CYBLE-473142-01 Preliminary Page 32 of 34CYBLE-473142-01Acronyms Document ConventionsUnits of MeasureTable 24. Acronyms Used in this DocumentAcronym DescriptionBLE Bluetooth Low EnergyBluetooth SIG Bluetooth Special Interest GroupCE European ConformityCSA Canadian Standards AssociationEMI electromagnetic interferenceESD electrostatic dischargeFCC Federal Communications CommissionGPIO general-purpose input/outputISED Innovation, Science and Economic Devel-opment (Canada)IDE integrated design environmentKC Korea CertificationMIC Ministry of Internal Affairs and Communications (Japan)PCB printed circuit boardRX receiveQDID qualification design IDSMTsurface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBsTCPWM timer, counter, pulse width modulator (PWM)TUV Germany: Technischer Überwachungs-Verein (Technical Inspection Association)TX transmitTable 25. Units of MeasureSymbol Unit of Measure°C degree CelsiuskV kilovoltmA milliamperesmm millimetersmV millivoltμA microamperesμm micrometersMHz megahertzGHz gigahertzVvolt

Document Number: CYBLE-473142-01 Preliminary Page 33 of 34CYBLE-473142-01Document History Page Document Title: CYBLE-473142-01 EZ-BLE™ Module with HomeKitDocument Number: CYBLE-473142-01 PreliminaryRevision ECN Orig. of ChangeSubmission Date Description of ChangePRELIM DSO 12/26/2017 Datasheet for CYBLE-473142-01 module.

Navigation menu