Cypress Semiconductor 3028 This product is a Bluetooth wireless EZ-BT WICED Module User Manual CYBT 013033 01 EZ BT Module

Cypress Semiconductor This product is a Bluetooth wireless EZ-BT WICED Module CYBT 013033 01 EZ BT Module

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Document Number: 002-23238 Rev. PRELIMINARY Page 2 of 45PRELIMINARY CYBT-423028-02More InformationCypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you toquickly and effectively integrate the module into your design. ReferencesnOverview: EZ-BLE/EZ-BT Module Portfolio, Module RoadmapnDevelopment Kits:pCYBT-423028-EVAL, CYBT-423028-02 Evaluation BoardpCYW920719Q40EVB-01, Evaluation Kit for CYW20719 silicon devicenTest and Debug Tools:pCYSmart, Bluetooth® LE Test and Debug Tool (Windows)pCYSmart Mobile, Bluetooth® LE Test and Debug Tool (Android/iOS Mobile App)nKnowledge Base ArticlepKBA97095 - EZ-BLE™ Module PlacementpKBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modulespKBA210802 - Queries on BLE Qualification and Declaration ProcessespKBA218122 - 3D Model Files for EZ-BLE/EZ-BT ModulespDevelopment EnvironmentsWireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)Cypress' WICED® (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits(SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth® connectivity in system design. WICED Studio is the only SDK for the Internet of Things (ioT) that combines Wi-Fi and Bluetooth into a single integrated developmentenvironment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio alsoleverages many common industry standards.Technical SupportnCypress Community: Whether you’re a customer, partner or a developer interested in the latest Cypress innovations, the Cypress Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers around the world.nFrequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System.nVisit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.

Document Number: 002-23238 Rev. PRELIMINARY Page 3 of 45PRELIMINARY CYBT-423028-02ContentsOverview............................................................................ 4Functional Block Diagram ........................................... 4Module Description...................................................... 4Pad Connection Interface ................................................ 6Recommended Host PCB Layout ................................... 7Module Connections ........................................................ 9Connections and Optional External Components ..... 11Power Connections (VDD) ........................................ 11External Reset (XRES).............................................. 11HCI UART Connections ............................................ 12External Component Recommendation .................... 12Critical Components List ........................................... 14Antenna Design......................................................... 14Bluetooth Baseband Core ............................................. 15Power Management Unit................................................ 16Integrated Radio Transceiver ........................................ 17Transmitter Path........................................................ 17Receiver Path............................................................ 17Local Oscillator.......................................................... 17Microcontroller Unit ....................................................... 18On-Chip Flash ........................................................... 18External Reset........................................................... 18Peripheral and Communication Interfaces .................. 19I2C............................................................................. 19UART (HCI UART) Interface ..................................... 19Peripheral UART Interface ........................................ 19Serial Peripheral Interface......................................... 1932 kHz Crystal Oscillator........................................... 20ADC Port ................................................................... 21GPIO Ports................................................................ 21PWM.......................................................................... 21PDM Microphone....................................................... 22I2S Interface.............................................................. 22PCM Interface ........................................................... 23Security Engine ......................................................... 23Power Modes .................................................................. 24Firmware.......................................................................... 24Electrical Characteristics............................................... 25Core Buck Regulator................................................. 26Digital LDO................................................................ 26RF LDO ..................................................................... 26Digital I/O Characteristics.......................................... 27Bluetooth Silicon Current Consumption .................... 27Chipset RF Specifications ............................................. 28Timing and AC Characteristics ..................................... 30UART Timing............................................................. 30SPI Timing................................................................. 30BSC Interface Timing ................................................ 32Environmental Specifications ....................................... 36Environmental Compliance ....................................... 36RF Certification.......................................................... 36Safety Certification .................................................... 36Environmental Conditions ......................................... 36ESD and EMI Protection ........................................... 36Regulatory Information .................................................. 37FCC........................................................................... 37ISED.......................................................................... 38European Declaration of Conformity ......................... 39MIC Japan................................................................. 39Packaging........................................................................ 40Ordering Information...................................................... 42Acronyms........................................................................ 43Document Conventions ................................................. 43Units of Measure ....................................................... 43Document History Page................................................. 44Sales, Solutions, and Legal Information ...................... 45Worldwide Sales and Design Support....................... 45Products .................................................................... 45PSoC® Solutions ...................................................... 45Cypress Developer Community................................. 45Technical Support ..................................................... 45

Document Number: 002-23238 Rev. PRELIMINARY Page 4 of 45PRELIMINARY CYBT-423028-02OverviewFunctional Block DiagramFigure 1 illustrates the CYBT-423028-02 functional block diagram.Figure 1. Functional Block DiagramNote: General Purpose Input/Output pins shown in Figure 1 are configuratble to any specified input or output function in the SuperMux table detailed in Table 5 in the ModuleConnections section. Note: Connections shown in the above block diagram are maximum number of connections per function. The total number of GPIOs available on the CYBT-423028-02 is 17.Module DescriptionThe CYBT-423028-02 module is a complete module designed to be soldered to the applications main board. Module Dimensions and DrawingCypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selectionswill still guarantee that all mechanical specifications and module certifications are maintained. Any changes to the current BOM forthe CYBT-423028-02 will not be made until approval is provided by the end customer for this product. The CYBT-423028-02 will beheld within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).Table 1. Module Design DimensionsSee Figure 2 for the mechanical reference drawing for CYBT-423028-02.Dimension Item SpecificationModule dimensions Length (X) 11.00 ± 0.15 mmWidth (Y) 11.00 ± 0.15 mmAntenna location dimensions Length (X) 6.00 mmWidth (Y) 2.50 mmPCB thickness Height (H) 0.50 ± 0.10 mmShield height Height (H) 1.20 mmMaximum component height Height (H) 0.60 mm typicalTotal module thickness (bottom of module to top of shield) Height (H) 1.70 mm typical

Document Number: 002-23238 Rev. PRELIMINARY Page 5 of 45PRELIMINARY CYBT-423028-02Figure 2. Module Mechanical DrawingBottom View (Seen from Bottom)Side ViewTop View (See from Top)Notes1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.

Document Number: 002-23238 Rev. PRELIMINARY Page 6 of 45PRELIMINARY CYBT-423028-02Pad Connection InterfaceAs shown in the bottom view of Figure 2 on page 5, the CYBT-423028-02 has 28 connections to a host board via solder pads (SP).Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-423028-02 module. Figure 3. Solder Pad Dimensions (Seen from Bottom)To maximize RF performance, the host layout should follow these recommendations:1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) mustcontain no ground or signal traces. This keep out area requirement applies to all layers of the host board. 2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB traceantenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Pleaserefer to AN96841 for module placement best practices.3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module chip antenna maycontain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of thehost board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBT-423028-02 Chip AntennaTable 2. Connection DescriptionName Connections Connection Type Pad Length Dimension Pad Width Dimension Pad PitchSP 28 Solder Pad 0.86 mm 0.51 mm 0.91 mmSolder Pad Connections (Seen from Bottom)Optional Host PCB Keep Out AreaAround Chip Antenna(Seen from Bottom)

Document Number: 002-23238 Rev. PRELIMINARY Page 7 of 45PRELIMINARY CYBT-423028-02Recommended Host PCB LayoutFigure 5, Figure 6, Figure 7, and Ta ble 3 provide details that can be used for the recommended host PCB layout pattern for theCYBT-423028-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.11 mm (0.56 mm from center of the pad oneither side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed usingeither Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 5. CYBT-423028-02 Host Layout (Dimensioned) Figure 6. CYBT-423028-02 Host Layout (Relative to Origin)Top View (Seen on Host PCB)Top View (Seen on Host PCB)

Document Number: 002-23238 Rev. PRELIMINARY Page 8 of 45PRELIMINARY CYBT-423028-02Table 3 provides the center location for each solder pad on the CYBT-423028-02. All dimensions are referenced to the center of thesolder pad. Refer to Figure 7 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference LocationSolder Pad(Center of Pad)Location (X,Y) from Orign (mm)Dimension from Orign (mils)1 (0.31, 2.79) (12.20, 109.84)2 (0.31, 3.71) (12.20, 146.06)3 (0.31, 4.62) (12.20, 181.89)4 (0.31, 5.54) (12.20, 218.11)5 (0.31, 6.45) (12.20, 253.94)6 (0.31, 7.37) (12.20, 290.16)7 (0.31, 8.28) (12.20, 325.98)8 (0.31, 9.19) (12.20, 361.81)9 (0.31, 10.11) (12.20, 398.03)10 (1.39,10.69) (54.72, 420.87)11 (2.30,10.69) (90.55, 420.87)12 (3.21,10.69) (126.38, 420.87)13 (4.13,10.69) (162.60, 420.87)14 (5.04,10.69) (198.42, 420.87)15 (5.96,10.69) (234.65, 420.87)16 (6.87,10.69) (270.47, 420.87)17 (7.79,10.69) (306.69, 420.87)18 (8.70,10.69) (342.52, 420.87)19 (9.61,10.69) (378.35, 420.87)20 (10.69,10.11) (420.87, 398.03)21 (10.69,9.19) (420.87, 361.81)22 (10.69,8.28) (420.87, 325.98)23 (10.69,7.37) (420.87, 290.16)24 (10.69,6.45) (420.87, 253.94)25 (10.69,5.54) (420.87, 218.11)26 (10.69,4.62) (420.87, 181.89)27 (10.69,3.71) (420.87, 146.06)28 (10.69,2.79) (420.87, 109.84)Top View (Seen on Host PCB)

Document Number: 002-23238 Rev. PRELIMINARY Page 9 of 45PRELIMINARY CYBT-423028-02Module ConnectionsTable 4 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections availableon the CYBT-423028-02 can be configured to any of the input or output funcitons listed in Table 5. Table 4 specifies any function thatis required to be used on a specific solder pad, and also identifies GPIOs that can be configured using the SuperMux. Table 4. CYBT-423028-02 Solder Pad Connection DefinitionsTable 5 details the available Input and Ouput functions that are configurable to any sodler pad in Table 4 that are marked as SuperMuxcapable. Pad Pad Name Silicon Pin Name XTALI/O ADC GPIO SuperMux Capable[2]1 GND GND Ground2 HOST_WAKE BT_HOST_WAKE A signal from the CYBT-423028-02 module to the host indicating that the Bluetooth device requires attention.3 UART_RXD BT_UART_RXD UART (HCI UART) Receive Data Only4 UART_TXD BT_UART_TXD UART (HCI UART) Transmit Data Only5 UART_RTS_N BT_UART_RTS_N UART (HCI UART) Request To Send Output Only6 UART_CTS_N BT_UART_CTS_N UART (HCI UART) Clear To Send Input Only7P2 P2 - - 33 see Table 58 VCC VDDIO Power Supply Input (1.76V ~ 3.63V)9P6 P6 - - 33 see Table 510 GND GND Ground11 XRES RST_N External Reset (Active Low)12 P33 P33 - IN6 33 see Table 513 P25 P25 - - 33 see Table 514 P26 P26 - - 33 see Table 515 P38 P38 - IN1 33 see Table 516 P34/P35/P36 P34P35P36 -IN5 (P34)IN4 (P35)IN3 (P36)3 (P34/P35/P36) 3 see Table 517 P1 P1 - IN28 33 see Table 518 P0 P0 - IN29 33 see Table 519 P29 P29 - IN10 33 see Table 520 P13/P23/P28 P13P23P28 -IN22 (P13)IN12 (P23)IN11 (P28)3(P13/P23/P28) 3 see Table 521 P10/P11 P10P11 -IN25 (P10)IN24 (P11) 3 (P10/P11) 3 see Table 522 P17 P17 - IN18 33 see Table 523 P7 P7 - - 3-24 P4 P4 - - 3-25 P16 P16 - IN19 3-26 XTALI_32K/P15[3] XTALI_32KP15 External Oscillator Input (32KHz) IN20 (P15) 3(P15) 3(P15), see Table 527 XTALO_32K XTALO_32K External Oscillator Output (32KHz) -- -28 GND GND GroundNote2. The CYBT-423028-02 can configure GPIO connections to any Input/Output function described in Table 5. 3. P15 should not be driven high externally while the part is held in reset (it can be floating or driven low). Failure to do so may cause some current to flow through P15 until the device comes out of reset.

Document Number: 002-23238 Rev. PRELIMINARY Page 10 of 45PRELIMINARY CYBT-423028-02Table 5. GPIO SuperMux Input FunctionsFunction Input or Output Function Type GPIOs Required Function Connection DescriptionSWD Input Serial Communication and Debug 2SWDCK, Serial Wire Debugger ClockInput/Output SWDIO, Serial Wire Debugger I/OSPI 1 Input/Output Serial Communication(Master or Slave) 4 ~ 7SPI 1 ClockSPI 1 Chip SelectSPI 1 MOSISPI 1 MISOSPI 1 I/O 2 (Quad SPI)SPI 1 I/O 3 (Quad SPI)SPI 1 InterruptSPI 2 Input/Output Serial Communication(Master or Slave) 4 ~ 7SPI 2 ClockSPI 2 Chip SelectSPI 2 MOSISPI 2 MISOSPI 2 I/O 2 (Quad SPI)SPI 2 I/O 3 (Quad SPI)SPI 2 InterruptPUARTInput Serial Communication Input4Periperal UART RXPeripheral UART CTSOutput Serial Communication Output Peripheral UART TXPeripheral UART RTSI2C Input/Output Serial Communication(Master or Slave) 2I2C ClockI2C DataI2C 2 Input/Output Serial Communication(Master or Slave) 2I2C 2 ClockI2C 2 DataPCM In Input Audio Input Communication 3PCM InputPCM ClockPCM SyncPCM Out Output Audio Output Communication 3PCM OutputPCM ClockPCM SyncI2S In Input Audio Input Communication 3I2S DI, Data InputI2S WS, Word SelectI2S ClockI2S Out Ouput Audio Output Communication 3I2S DO, Data OutputI2S WS, Word SelectI2S ClockPDM Input Microphone 1 ~ 2 PDM Input Channel 1PDM Input Channel 2PWM Output Pulse Width Modulator 1 ~ 6PWM Channel 0PWM Channel 1PWM Channel 2PWM Channel 3PWM Channel 4PWM Channel 5ACLK Output Auxiliary Clock 1 ~ 2 Auxiliary Clock 0 (ACLK0)Auxiliary Clock 1 (ACLK1)HIDOFF Output HID-OFF Indicator 1 HID-OFF Indicator to host

Document Number: 002-23238 Rev. PRELIMINARY Page 11 of 45PRELIMINARY CYBT-423028-02Connections and Optional External ComponentsPower Connections (VDD)The CYBT-423028-02 contains one power supply connection, VDD.VDD accepts a supply input of 1.76 V to 3.63 V. Table 12 provides this specification. The maximum power supply ripple for this powerconnection is 100 mV, as shown in Table 12. Considerations and Optional Components for Brown Out (BO) ConditionsPower supply design must be completed to ensure that the CYBT-423028-02 module does not encounter a Brown Out condition,which can lead to unexpected funcitonality, or module lock up. A Brown Out condition may be met if power supply provided to themodule during power up or reset is in the range shown below: VIL ≤ VDD ≤ VIHRefer to Table 17 for the VIL and VIH specifications. System design should ensure that the condition above is not encountered when power is removed from the system. In the event thatthis cannot be guaranteed (i.e. battery installation, high value power capacitors with slow discharge), it is recommended that anexternal voltage detection device be used to prevent the Brown Out voltage range from occuring during power removal. Please referto Figure 8 for the recommended circuit design when using an external voltage detection IC.Figure 8. Reference Circuit Block Diagram for External Voltage Detection ICIn the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling themodule will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issuesthat cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition. External Reset (XRES)The CYBT-423028-02 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. Thisaction can also be envoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal,which is an input to the CYBT-423028-02 module (solder pad 11). The CYBT-423028-02 module does not require an external pull-upresistor on the XRES input During power on operation, the XRES connection to the CYBT-423028-02 is required to be held low 50 ms after the VDD power supplyinput to the module is stable. This can be accomplished in the following ways: nThe host device can connect a GPIO to the XRES of Cypress CYBT-423028-02 module and pull XRES low until VDD is stable.XRES is recommended to be released 50 ms after VDD is stable.nIf the XRES connection of the CYBT-423028-02 module is not used in the application, a 0.33 uF capacitor may be connected to theXRES solder pad of the CYBT-423028-02 in order to delay the XRES release. The capacitor value for this recommended imple-mentation is approximate, and the exact value may differ depending on the VDD power supply ramp time of the system. The capacitorvalue should result in an XRES release timing of at least 50 ms after VDD stability. nThe XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable.Refer to Figure 11 on page 18 for XRES operating and timing requirements during power on events.

Document Number: 002-23238 Rev. PRELIMINARY Page 12 of 45PRELIMINARY CYBT-423028-02HCI UART ConnectionsThe recommendations in this section apply to the HCI UART (Solder Pads 3, 4, 5, and 6). For full UART functionality, all UART signalsmust be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired orcapable, then the following connection considerations should be followed for UART RTS and CTS: nUART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on. nUART CTS: Must be pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to themodule.External Component RecommendationPower Supply CircuitryIt is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite beadbetween the supply and the module connection can be included. The ferrite bead should be positioned as close as possible to themodule pad connection. If used, the recommended ferrite bead value is 330 Ω, 100 MHz. (Murata BLM21PG331SN1D).

Document Number: 002-23238 Rev. PRELIMINARY Page 13 of 45PRELIMINARY CYBT-423028-02Figure 9 illustrates the CYBT-423028-02 schematic.Figure 9. CYBT-423028-02 Schematic Diagram

Document Number: 002-23238 Rev. PRELIMINARY Page 14 of 45PRELIMINARY CYBT-423028-02Critical Components ListTable 6 details the critical components used in the CYBT-423028-02 module.Table 6. Critical Component ListAntenna DesignTable 7 details the chip antenna used in the CYBT-423028-02 module. Table 7. Chip Antenna SpecificationsComponent Reference Designator DescriptionSilicon U2 40-pin QFN Bluetooth Silicon Device - CYW20719Chip Antenna A1 Antennam, 2.4 GHzCrystal Y1 24.000 MHz, 12PFItem DescriptionFrequency Range 2400 – 2500 MHzPeak Gain -1.0 dBi typicalReturn Loss 10.0 dB typical

Document Number: 002-23238 Rev. PRELIMINARY Page 16 of 45PRELIMINARY CYBT-423028-02Power Management UnitFigure 10 shows the CYBT-423028-02 power management unit (PMU) block diagram. The CYBT-423028-02 includes an integrated buck regulator, a bypass LDO, a capless LDO, for digital circuits and 1.2V LDO for RF. The bypass LDO automatically takes over from the buck once Vbat supply falls below 2.1V. The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions.Figure 10. Default Usage Mode

Document Number: 002-23238 Rev. PRELIMINARY Page 17 of 45PRELIMINARY CYBT-423028-02Integrated Radio TransceiverThe CYBT-423028-02 has an integrated radio transceiver that has been designed to provide low power operation in the globallyavailable 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the require-ments to provide the highest communication link quality of service.Transmitter PathCYBT-423028-02 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.Digital ModulatorThe digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizesany frequency drift or anomalies in the modulation characteristics of the transmitted signal.Power AmplifierThe CYBT-423028-02 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.Receiver PathThe receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bitsynchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation inthe noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBT-423028-02 to beused in most applications without off-chip filtering.Digital Demodulator and Bit SynchronizerThe digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bitsynchronization algorithm.Receiver Signal Strength IndicatorThe radio portion of the CYBT-423028-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables thecontroller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whetherthe transmitter should increase or decrease its output power.Local OscillatorThe local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. TheCYBT-423028-02 uses an internal loop filter.

Document Number: 002-23238 Rev. PRELIMINARY Page 18 of 45PRELIMINARY CYBT-423028-02Microcontroller UnitThe CYBT-423028-02 includes a Cortex M4 (CM4) that can run at 96 MHz. The CM4 also includes a single precision IEEE-754compliant floating point unit (FPU). For details on the CM4 or the FPU please see the Cortex M4 manual. A standard serial wire debug(SWD) interface provides support for debugging. The CM4 runs the BT layers as well as any application code. 2 Mbytes of attached ROM have the core firmware as well as variousstack layers. 512 KBytes of RAM provide data storage and also the ability to run patch and application code. Additionally, 1 MByte offlash provide storage for configuration data and also support direct execution of application code and patches. The inclusion of coreFW, stack layers and various libraries in the on-board ROM allow for most of the flash and RAM to be used for data and applicationcode.Please see the firmware section for details on the architecture and layers that are included in the ROM.On-Chip FlashThe silicon device used in the CYBT-423028-02 module includes 1 MB of on-chip flash. This flash can be used for direct programexecution or for non-volatile data. Typical usage for the on-chip flash includes:nChip configurationnPatchesnPeer addresses and link keysnApplication codenApplication non-volatile datanProduct informationExternal ResetAn external active-low reset signal, XRES, can be used to put the CYBT-423028-02 in the reset state. An external voltage detectorreset IC with 50 ms delay is recommended on the XRES connection. The XRES must only be released after the VDDO supply volt-age level has been stabilized for 50 ms.Figure 11. Reset Timing

Document Number: 002-23238 Rev. PRELIMINARY Page 19 of 45PRELIMINARY CYBT-423028-02Peripheral and Communication InterfacesI2C The CYBT-423028-02 provides a 2-pin I2C compatible master interface to communicate with I2C compatible peripherals. The followingtransfer clock rates are supported are:n100 kHzn400 kHzn800 kHz (Not a standard I2C-compatible speed)n1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed)The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYBT-423028-02 are requiredon both the SCL and SDA pins configured for I2C operation. Cypress BSC does not support multimaster capability or flexible wait-stateinsertion by either master or slave devices.UART (HCI UART) InterfaceThe CYBT-423028-02 includes a UART interface for factory programming as well as when operating as a BT HCI device in a systemwith an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud ratesfrom 115200 bps to 3 Mbps typical rates are 115200, 921600, 1500000, and 3,000,000 bps although intermediate speeds are alsoavailable. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command.The CYBT-423028-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices iswithin ±5%. The CYBT-423028-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. Theinterface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.The CYBT-423028-02 can wake up the host as needed or allow the host to sleep via the HOST_WAKE signal (Pad 2). HOST_WAKEsignals can be enabled via a vendor specific command. The FW UART driver allows applications to select different baud rates. Peripheral UART InterfaceThe CYBT-423028-02 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed throughthe optional I/O ports, which can be configured individually and separately for each functional pin. The CYBT-423028-02 can map theperipheral UART to any GPIO. The Peripheral UART functions the same as the HCI UART, but with a 256-byte transmit and receiveFIFO. Serial Peripheral InterfaceThe CYBT-423028-02 has two independent SPI interfaces. Both interfaces support Single, Dual, and Quad mode SPI operations aswell as MIPI DBI-C Interface. Either interface can be a master or a slave. SPI2 can support only one slave. SPI1 has a 1024 bytetransmit and receive buffer which is shared with the host UART interface. SPI2 has a dedicated 256 byte transmit and recieve buffer.To support more flexibility for user applications, the CYBT-423028-02 has optional I/O ports that can be configured individually foreach functional pin. SPI IO voltage depends on VDD.Table 8. Common Baud Rate Examples, 24 MHz ClockBaud Rate (bps) DHBR DLBR Mode Error (%)3M 0xFF 0xF8 High rate 0.002M 0XFF 0XF4 High rate 0.001.5M 0X00 0XFF Normal 0.001M 0x44 0xFF Normal 0.00921600 0x55 0xFF Normal 0.16460800 0x22 0xFD Normal 0.16230400 0x44 0xFA Normal 0.16115200 0x00 0xF3 Normal 0.1638400 0x01 0xD9 Normal 0.00

Document Number: 002-23238 Rev. PRELIMINARY Page 20 of 45PRELIMINARY CYBT-423028-0232 kHz Crystal OscillatorThe CYBT-423028-02 utlizes the built-in Local Oscillator (LO) on the CYW20719 silicon device for 32kHz timing. The accuracy of theLO is +/- 500 ppm. The use of an external XTAL oscillator is optional. CYBT-423028-02 includes external XTAL oscilator connectionsfor applications requiring higher timing accuracy. Figure 12 shows an external 32 kHz XTAL oscillator with external components andTable 9 lists the the recommended external oscillator’s characteristics. This oscillator input can be operated with a 32 kHz or 32.768kHz crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 MΩ and C1 =C2 = ~6 pF. The values of C1 and C2 are used to fine-tune the oscillator.Figure 12. 32 kHz Oscillator Block DiagramTable 9. XTAL Oscillator CharacteristicsParameter Symbol Conditions Minimum Typical Maximum UnitOutput frequency Foscout – – 32.768 – kHzFrequency tolerance – Crystal-dependent – 100 – ppmStart-up time Tstartup – – 500 – msXTAL drive level Pdrv For crystal selection – – 0.5 μWXTAL series resistance Rseries For crystal selection – – 70 kΩXTAL shunt capacitance Cshunt For crystal selection – – 2.2 pF

Page 21 of 45Document Number: 002-23238 Rev. PRELIMINARYPRELIMINARY CYBT-423028-02ADC PortThe ADC is a Σ-Δ ADC core designed for audio (13 bits) and DC (10 bits) measurement. It operates at a 12 MHz and has 11 solderpad connections that can act as input channels. The internal bandgap reference has ±5% accuracy without calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC mode.The following CYBT-423028-02 module solder pads can be used as ADC inputs:n Pad 12: P33, ADC Input Channel 6n Pad 15: P38, ADC Input Channel 1n Pad 16: P34/P35/P36, ADC Input Channels 5/4/3 respectively; NOTE: only one ADC input on this solder pad can be active at agiven time.n Pad 17: P1, ADC Input Channel 28n Pad 18: P0, ADC Input Channel 29n Pad 19: P29, ADC Input Channel 10n Pad 20: P13/P23/28, ADC Input Channels 22/12/11 respectively; NOTE: only one ADC input on this solder pad can be active at agiven time.nPad 21: P10/P11, ADC Input Channels 25/24 respectively; NOTE: only one ADC input on this solder pad can be active at a given time. nPad 22: P17, ADC Input Channel 18nPad 25: P16, ADC Input Channel 19nPad 26: P15, ADC Input Channel 20GPIO PortsThe CYBT-423028-02 has a maximum of 17 general-purpose I/Os (GPIOs). All GPIOs support programmable pull-ups and pull-downswith an internal pull-up/pull-down resistor value of ~45 Kohm. All GPIOs are capable of sourcing or sinking up to 8 mA at 3.3V or 4mA at 1.8V. Pad 14 (P26) and Pad 19 (P29) are capable of driving up to 16 mA at 3.3V or 8 mA at 1.8V and include PWM functionalityfor LED dimming.nThe following GPIOs are available on the CYBT-423028-02 module: pP0-P2, P4, P6, P7, P16, P17, P25, P26, P29, P33, and P38pP10/P11 (Double bonded connection on the CYBT-423028-02 module, only one of two is available)pP13/P23/P28 (Triple bonded connection on the CYBT-423028-02 module, only one of three is available)pP15/XTALI_32K (Double bonded pin on the CYBT-423028-02 module, only one of two is available)pP34/P35/P36 (Triple bonded pin on the CYBT-423028-02 module, only one of three is available)pP19, P20 and P39 are reserved for system use. Please do not use those 3 GPIOs.On double and triple bonded connections, only one of the connections can be used at a given time. When a certain GPIO is selected,the other GPIOs bonded to the same connection must be configured to input with output disable.PWMThe CYBT-423028-02 has six internal PWMs. The PWM module consists of the following:nPWM0–5. Each of the six PWM channels contains the following registers:p16-bit initial value register (read/write)p16-bit toggle register (read/write)p16-bit PWM counter value register (read)nPWM configuration register shared among PWM0–5 (read/write). This 18-bit register is used:pTo configure each PWM channelpTo select the clock of each PWM channel pTo change the phase of each PWM channelFigure 13 shows the structure of one PWM.

Document Number: 002-23238 Rev. PRELIMINARY Page 22 of 45PRELIMINARY CYBT-423028-02Figure 13. PWM Block DiagramPDM MicrophoneThe CYBT-423028-02 accepts a ΣΔ-based one-bit pulse density modulation (PDM) input stream and outputs filtered samples at either8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generatedigital signals. The digital signal passes through the chip IO and MUX inputs using an auxADC signal. The PDM shares the filter pathwith the auxADC. Two types of data rates can be supported:n8 kHzn16 kHzThe external digital microphone takes in a 2.4 MHz clock generated by the CYBT-423028-02 and outputs a PDM signal which isregistered by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable controlbit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible. I2S InterfaceThe CYBT-423028-02 supports a single I2S digital audio port. with both master and slave modes. The I2S signals are:nI2S Clock: I2S SCKnI2S Word Select: I2S WSnI2S Data Out: I2S DOnI2S Data In: I2S DII2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output. The channelword length is 16 bits and the data is justified so that the MSN of the left-channel data is aligned with the MSB of the I2S bus, per I2SSpecifications. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the fallingedge of bit clock. Left Channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high.Data bits sent by the CYBT-423028-02 are synchronized with the falling edge of I2S SCK and should be sampled by the receiver onthe rising edge of the I2S SCK.NOTE: The PCM interface shares HW with the I2S interface and only one can be used at a given time.

Document Number: 002-23238 Rev. PRELIMINARY Page 23 of 45PRELIMINARY CYBT-423028-02PCM InterfaceThe CYBT-423028-02 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In mastermode, the CYBT-423028-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by anothermaster on the PCM interface and are inputs to the CYBT-423028-02.The configuration of the PCM interface may be adjusted by thehost through the use of vendor-specific HCI commands.NOTE: The PCM interface shares HW with the I2S interface and only one can be used at a given time. Slot MappingThe CYBT-423028-02 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM Interface. These threechannels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sampleinterval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCMdata from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allowother devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCMclock during the last bit of the slot.Frame SynchronizationThe CYBT-423028-02 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchro-nization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width andis synchronized to the rising edge of the bit clock. The PCGM slave looks for a high on the falling edge of the bit clock and expectsthe first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronizationsignal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincidentwith the first bit of the first slot.Data FormattingThe CYBT-423028-02 may be configured to generate and accept several different data formats. For conventional narrow band speechmode, the CYBT-423028-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured tosupport various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, asign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.Burst PCM ModeIn this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation andsave current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated withan HCI command from the host.Security EngineThe CYBT-423028-02 includes a hardware security accelerator which greatly decreases the time required to perform typical securityoperations. Access to the hardware block is provided via a firmware interface (see firmware documentation for details).Thie securityengine includes:nPublic key acceleration (PKA) cryptographynAES-CTR/CBC-MAC/CCM accelerationnSHA2 message hash and HMAC accelerationnRSA encryption and decryption of modulus sizes up to 2048 bitsnElliptic curve Diffie-Hellman in prime field GF(p)Random Number GeneratorThis hardware block is used for key generation for Bluetooth.Note: Availability for use by the application is subject to the support in WICED Studio.Note: The Random Number Generator block must be warmed up prior to use. A delay of 500 ms from cold boot is necessary prior tousing the Random Number Generator.

Document Number: 002-23238 Rev. PRELIMINARY Page 24 of 45PRELIMINARY CYBT-423028-02Power ModesThe CYBT-423028-02 support the following HW power modes are supported:nActive mode: Normal operating mode in which all peripherals are available and the CPU is active.nIdle mode: In this mode, the CPU is in Wait for Interrupt (WFI) and the HCLK, which is the high frequency clock derived from themain crystal oscillator, is running at a lower clock speed. Other clocks are active and the state of the entire chip is retained.nPDS mode: PDS mode is an extension of the PMU Sleep wherein most of the peripherals such as UART, and SPI are turned off.The entire memory is retained, and on wakeup the execution resumes from where it was paused.nShut Down Sleep (SDS): Everything is turned off except IO Power Domain, RTC, and the LPO. The device can come out of thismode either due to BT activity or an external interrupt. Before going into this mode, the application can store some bytes of datainto the Always On RAM (AON). When the device comes out of this mode, the data from AON is restored. After waking from SDS,the application will start from the beginning (warmboot) and has to restore its state based on information stored in AON. In the SDSmode, a single BT task with no data activity, such as an ACL connection, BLE connection, or BLE advertisement can be performed.nHIDOFF (Timed-Wake) mode: The device can enter this mode asynchronously. That is, the application can force the device intothis mode at any time. IO Power Domain, RTC, and the LPO are the only active blocks. A timer that runs off the LPO is used towake the device up after a predetermined fixed time. This mode requires the use of an external XTAL oscillator. nHID-OFF (External Interrupt Waked) mode: This mode is similar to Timed-Wake, but in HID-OFF mode, the LPO and RTC areturned off. The only wakeup source in HID-OFF mode is an external interrupt.FirmwareThe CYBT-423028-02 ROM firmware runs on a real time operating system and handles the programming and configuration of allon-chip hardware functions. This include the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP and SDP layers. The ROM includesdrivers for on-chip peripherals. In addition, the ROM also handles on-chip power management functions including transitions betweendifferent power modes. The CYBT-423028-02 is supported by the Cypress WICED Studio platform. WICED releases provide the latest ROM patches, drivers,and sample applications allowing customized applications using the CYBT-423028-02 to be built quickly and efficiently.Please refer to WICED documentation for details on the firmware architecture and how to write applications/profiles using theCYBT-423028-02.

Document Number: 002-23238 Rev. PRELIMINARY Page 25 of 45PRELIMINARY CYBT-423028-02Electrical CharacteristicsThe absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even if theselimits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolutemaximum conditions for extended periods can adversely affect long-term reliability of the device.The CYBT-423028-02 uses an onboard low voltage detector to shut down the part when supply voltage (VDD) drops below operatingrange.Table 13. Power Supply SpecificationsTable 10. Silicon Absolute Maximum RatingsRequirement Parameter Specification UnitMin. Nom. Max.Maximum Junction Temperature – – 125 °CVDD IO –0.5 – 3.795 VVDD RF –0.5 – 1.38 VVDDBAT3V –0.5 – 3.795 VDIGLDO_VDDIN1P5 –0.5 – 1.65 VRFLDO_VDDIN1P5 –0.5 – 1.65 VPALDO_VDDIN_5V –0.5 – 3.795 VMIC_AVDD –0.5 – 3.795 VTable 11. ESD/LatchupRequirement Parameter Specification UnitMin. Nom. Max.ESD Tolerance HBM (Silicon) –2000 – 2000 VESD Tolerance CDM (Silicon) –500 – 500 VESD Tolerance CDM (Silicon, Corners) –750 – 750 VLatch-up – 200 – mATable 12. Power Supply SpecificationsParameter Conditions Min. Typical Max. UnitVDD input Module Input 1.76 3.3 3.63 VVDD Ripple Module Input – – 100 mVVBAT Input Internal to Module (not accessible) 1.62 3.3 3.6 VPMU turn-on time VBAT is ready. – – 300 μsParameter Min. Typical Max. UnitVSHUT 1.625 1.7 1.76 V

Document Number: 002-23238 Rev. PRELIMINARY Page 26 of 45PRELIMINARY CYBT-423028-02Core Buck RegulatornMinimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.nMaximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes any decoupling capacitors connected at the load side, if any.Digital LDORF LDOTable 14. Silicon Core Buck RegulatorParameter Conditions Min. Typ. Max. UnitInput supply voltage DC, VBAT DC voltage range inclusive of disturbances 1.76 3.0 3.63 VCBUCK output current LPOM only – – 65 mAOutput voltage range Programmable, 30mV/stepdefault = 1.2V (bits=0000) 1.21.261.5 VOutput voltage DC accuracy Includes load and line regulation –2 – +2 %LPOM efficiency (high load) – 85 – %LPOM efficiency (low load) – 80 – %Input supply voltage ramp-up time 0 to 3.3V 40 – – ?sTable 15. Digital LDOParameter Conditions Min. Typ. Max. UnitInput supply voltage, Vin Minimum Vin=Vo+0.12V requirement must be met under maximum load. 1.2 1.2 1.6 VNominal output voltage,Vo Internal default setting – 1.1 – VDropout voltage At maximum load – – 120 mVTable 16. RF LDOParameter Conditions Min. Typ. Max. UnitInput supply voltage, Vin Min Vin=Vo+0.15V = 1.35V (for Vo=1.2V)Dropout voltage requirement must be met under maximum load.1.21.261.5 VExternal Input supply voltage RF LDO supplied via external supply – 1.35 – VNominal output voltage,Vo Internal default bit setting 000 – 1.2 – VDropout voltage At maximum load – – 150 mVOutput current Operating Voltage range 0.1 – 25 mAQuiescent current No load – 44 – μAIn-rush current Vin=Vo+0.15V to 1.5V, Co=2.2 μF, no load – – 100 mANote: Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.

Document Number: 002-23238 Rev. PRELIMINARY Page 27 of 45PRELIMINARY CYBT-423028-02Digital I/O CharacteristicsBluetooth Silicon Current ConsumptionIn Table 18, current consumption measurements are taken at module input VDD = 3.0V.Table 17. Digital I/O CharacteristicsCharacteristics Symbol Minimum Typical Maximum UnitInput low voltage (VDD = 3V) VIL ––0.8VInput high voltage (VDD = 3V) VIH 2.0 – – VInput low voltage (VDD = 1.8V) VIL ––0.6VInput high voltage (VDD = 1.8V) VIH 1.1 – – VOutput low voltage VOL ––0.4VOutput high voltage VOH VDDO – 0.4V – – VInput low current IIL ––1.0μAInput high current IIH ––1.0μAOutput low current (VDD = 3V, VOL = 0.4V) IOL ––2.0mAOutput low current (VDD = 3V, VOL = 1.8V) IOL ––2.0mAOutput high current (VDD = 3V, VOH = 2.6V) IOH ––4.0mAOutput high current (VDD = 1.8V, VOH = 1.4V) IOH ––2.0mAInput capacitance CIN ––0.4pFTable 18. SIlicon Current Consumption BT/LEOperational Mode Conditions Typical UnitHCI 48 MHz with Pause 1.1 mA48 MHz Without Pause 2.2 mARX Continuous RX 5.9 mATX Continuous TX - 0 dBm 5.6 mAPDS 61 μAHID-Off (SDS) 32 KHz xtal and 16 KB Retention RAM on 1.6 μAAdvertising Unconnectable - 1 sec 14 μAConnectable Undirected - 1 sec 17 μALE Connection - SDS Master - 1 sec TBD μASlave - 1 sec TBD μAPage Scan - PDS Interlaced - R1 122 μASniff - PDS 500 ms Sniff, 1 attempt, 0 timeout - Master 132 μA500 ms Sniff, 1 attempt, 0 timeout - Slave 138 μABi-Directional Data Exchange Continuous DM5 or DH5 packets - Master or Slave 6.9 mA

Document Number: 002-23238 Rev. PRELIMINARY Page 28 of 45PRELIMINARY CYBT-423028-02Chipset RF SpecificationsTable 19 and Table 20 apply to single-ended industrial temperatures. Unused inputs are left open.Table 19. Chipset Receiver RF SpecificationsParameter Mode and Conditions Min Typ Max UnitReceiver SectionFrequency range – 2402 – 2480 MHzRX sensitivity GFSK, BDR GFSK 0.1% BER, 1 Mbps – –92.011. The receiver sensitivity is measured at BER of 0.1% on the device interface.–dBmMaximum input – –20 – – dBmInterference PerformanceC/I cochannel GFSK, BDR GFSK 0.1% BER22. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).11.0 – – dBC/I 1 MHz adjacent channel GFSK, BDR GFSK 0.1% BERb0.0 – – dBC/I 2 MHz adjacent channel GFSK, BDR GFSK 0.1% BERb–30.0 – – dBC/I ≥ 3 MHz adjacent channel GFSK, BDR GFSK 0.1% BER33. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).–40.0 – – dBC/I image channel GFSK, BDR GFSK 0.1% BERb–9.0 – – dBC/I 1 MHz adjacent to image channel GFSK, BDR GFSK 0.1% BERb–20.0 – – dBOut-of-Band Blocking Performance (CW)c30 MHz to 2000 MHz BDR GFSK 0.1% BER – –10.0 – dBm2000 MHz to 2399 MHz BDR GFSK 0.1% BER – –27 – dBm2498 MHz to 3000 MHz BDR GFSK 0.1% BER – –27 – dBm3000 MHz to 12.75 GHz BDR GFSK 0.1% BER – –10.0 – dBmIntermodulation Performance44. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1, interferer 2 is –39 dBm Bluetooth-modulated signal at frequency f2, f0 = 2*f1 – f2, and |f2 – f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4. BT, interferer signal level BDR GFSK 0.1% BER – – –39.0 dBmSpurious Emissions30 MHz to 1 GHz – – – –57.0 dBm1 GHz to 12.75 GHz – – – –55.0 dBm

Document Number: 002-23238 Rev. PRELIMINARY Page 29 of 45PRELIMINARY CYBT-423028-02Table 20. Chipset Transmitter RF SpecificationsParameter Min Typ Max UnitTransmitter SectionFrequency range 2402 – 2480 MHzClass 2: GFSK Tx power – 2.0 4.0 dBm20 dB bandwidth – 930 1000 kHzAdjacent Channel Power|M – N| = 2 – – –20 dBm|M – N| ≥ 3 – – –40 dBmOut-of-Band Spurious Emission30 MHz to 1 GHz – – –36.0 dBm1 GHz to 12.75 GHz – – –30.0 dBm1.8 GHz to 1.9 GHz – – –47.0 dBm5.15 GHz to 5.3 GHz – – –47.0 dBmLO PerformanceInitial carrier frequency tolerance –75 – +75 kHzFrequency DriftDH1 packet –25 – +25 kHzDH3 packet –40 – +40 kHzDH5 packet –40 – +40 kHzDrift rate –20 20 kHz/50 µsFrequency DeviationAverage deviation in payload(sequence used is 00001111) 140 – 175 kHzMaximum deviation in payload(sequence used is 10101010) 115 – – kHzChannel spacing – 1 – MHzTable 21. BLE Silicon RF SpecificationsParameter Conditions Minimum Typical Maximum UnitFrequency range N/A 2402 – 2480 MHzRx sensitivity11. Dirty Tx is Off.GFSK, BDR GFSK 0.1% BER 0.1% BER, 1 Mbps ––95.5– dBmTx power N/A – 2.0 4.0 dBmMod Char: Delta F1 average N/A 225 255 275 kHzMod Char: Delta F2 max22. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.N/A 99.9 – – %Mod Char: Ratio N/A 0.8 0.95 – %

Document Number: 002-23238 Rev. PRELIMINARY Page 30 of 45PRELIMINARY CYBT-423028-02Timing and AC CharacteristicsIn this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.UART TimingFigure 14. UART TimingSPI TimingThe SPI interface can be clocked up to 24 MHz.Table 23 and Figure 15 show the timing requirements when operating in SPI Mode 0 and 2.Table 22. UART Timing SpecificationsReference Characteristics Min. Typ. Max. Unit1 Delay time, UART_CTS_N low to UART_TXD valid. – – 1.50 Bit periods2 Setup time, UART_CTS_N high before midpoint of stop bit. – – 0.67 Bit periods3 Delay time, midpoint of stop bit to UART_RTS_N high. – – 1.33 Bit periodsTable 23. SPI Mode 0 and 2Reference Characteristics Min. Max. Unit1 Time from master assert SPI_CSN to first clock edge 45 – ns2 Hold time for MOSI data lines 12 ½ SCK ns3 Time from last sample on MOSI/MISO to slave deassert SPI_INT 0 100 ns4 Time from slave deassert SPI_INT to master deassert SPI_CSN 0 – ns5 Idle time between subsequent SPI transactions 1 SCK – ns

Document Number: 002-23238 Rev. PRELIMINARY Page 31 of 45PRELIMINARY CYBT-423028-02Figure 15. SPI Timing, Mode 0 and 2Table 24 and Figure 16 show the timing requirements when operating in SPI Mode 1 and 3.Table 24. SPI Mode 1 and 3Reference Characteristics Min. Max. Unit1 Time from master assert SPI_CSN to first clock edge 45 – ns2 Hold time for MOSI data lines 12 ½ SCK ns3 Time from last sample on MOSI/MISO to slave deassert SPI_INT 0 100 ns4 Time from slave deassert SPI_INT to master deassert SPI_CSN 0 – ns5 Idle time between subsequent SPI transactions 1 SCK – ns

Document Number: 002-23238 Rev. PRELIMINARY Page 32 of 45PRELIMINARY CYBT-423028-02Figure 16. SPI Timing, Mode 1 and 3BSC Interface TimingThe specifications in Table 25 references Figure 17.Table 25. BSC Interface Timing Specifications (up to 1 MHz)Reference Characteristics Minimum Maximum Unit1 Clock frequency – 100 kHz40080010002 START condition setup time 650 – ns3 START condition hold time 280 – ns4 Clock low time 650 – ns5 Clock high time 280 – ns6 Data input hold time11. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.0 – ns7 Data input setup time 100 – ns8 STOP condition setup time 280 – ns9 Output valid from clock – 400 ns10 Bus free time22. Time that the CBUS must be free before a new transaction can start.650 – ns

Document Number: 002-23238 Rev. PRELIMINARY Page 33 of 45PRELIMINARY CYBT-423028-02Figure 17. BSC Interface Timing Diagram

Document Number: 002-23238 Rev. PRELIMINARY Page 34 of 45PRELIMINARY CYBT-423028-02Table 26. Timing for I2S Transmitters and ReceiversTransmitter ReceiverNotesLower LImit Upper Limit Lower Limit Upper LimitMin Max Min Max Min Max Min MaxClock Period T Ttr –––Tr–––1Master Mode: Clock generated by transmitter or receiverHIGH tHC 0.35Ttr – – – 0.35Ttr –––2LOWtLC 0.35Ttr – – – 0.35Ttr –––2Slave Mode: Clock accepted by transmitter or receiverHIGH tHC –0.35Ttr –––0.35Ttr ––3LOW tLC –0.35Ttr –––0.35Ttr ––3Rise time tRC – – 0.15Ttr ––– – 4TransmitterDelay tdtr –––0.8T––––5Hold time thtr 0–––––––4ReceiverSetup time tsr ––––0.2Ttr –––6Hold time thr ––––0.2Ttr –––61. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate.2.At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T.3.In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used.4.Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr.5. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time.6. The data setup and hold time must not be less than the specified receiver setup and hold time.

Document Number: 002-23238 Rev. PRELIMINARY Page 35 of 45PRELIMINARY CYBT-423028-02Figure 18. I2S Transmitter TimingFigure 19. I2S Receiver Timing

Document Number: 002-23238 Rev. PRELIMINARY Page 36 of 45PRELIMINARY CYBT-423028-02Environmental SpecificationsEnvironmental ComplianceThis Cypress BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF)directives. The Cypress module and components used to produce this module are RoHS and HF compliant.RF CertificationThe CYBT-423028-02 module is certified under the following RF certification standards:nFCC: TBDnISED: TBDnMIC: TBDnCESafety CertificationThe CYBT-423028-02 module complies with the following safety regulations:nUnderwriters Laboratories, Inc. (UL): Filing E331901nCSAnTUVEnvironmental ConditionsTable 27 describes the operating and storage conditions for the Cypress BLE module.ESD and EMI ProtectionExposed components require special attention to ESD and electromagnetic interference (EMI).A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosurenear the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.Table 27. Environmental Conditions for CYBT-423028-02Description Minimum Specification Maximum SpecificationOperating temperature −30 °C 85 °COperating humidity (relative, non-condensation) 5% 85%Thermal ramp rate – 10 °C/minuteStorage temperature –40 °C 85 °CStorage temperature and humidity – 110 °C at 85%ESD: Module integrated into system Components[4] –15 kV Air2.0 kV ContactNote4. This does not apply to the RF pins (ANT).

Document Number: 002-23238 Rev. PRELIMINARY Page 37 of 45PRELIMINARY CYBT-423028-02Regulatory InformationFCCFCC NOTICE:The device CYBT-423028-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitterapproval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This devicemay not cause harmful interference, and (2) This device must accept any interference received, including interference that may causeundesired operation.CAUTION:The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved byCypress Semiconductor may void the user's authority to operate the equipment.This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipmentgenerates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may causeharmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipmentoff and on, the user is encouraged to try to correct the interference by one or more of the following measures:nReorient or relocate the receiving antenna. nIncrease the separation between the equipment and receiver. nConnect the equipment into an outlet on a circuit different from that to which the receiver is connected. nConsult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visiblelabel on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as wellas the FCC Notice above. The FCC identifier is FCC ID: TBD.In any case the end product must be labeled exterior with “Contains FCC ID: TBD”.ANTENNA WARNING: This device is tested with a standard SMA connector and with the antenna listed in Table 7 on page 14. When integrated in the OEMsproduct, this fixed antenna requires installation preventing end-users from replacing them with non-approved antennas. Any antennanot in Table 7 on page 14 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 foremissions.RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approvedantenna in the previous.The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennasin Table 7 on page 14, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removalinstructions about the integrated radio module is not allowed.The radiated output power of CYBT-423028-02 with the integrated PCB trace antenna (FCC ID: TBD) is far below the FCC radiofrequency exposure limits. Nevertheless, use CYBT-423028-02 in such a manner that minimizes the potential for human contactduring normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided withtransmitter operating conditions for satisfying RF exposure compliance.

Document Number: 002-23238 Rev. PRELIMINARY Page 38 of 45PRELIMINARY CYBT-423028-02ISEDInnovation, Science and Economic Development (ISED) Canada CertificationCYBT-423028-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada. License: IC: TBDManufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensurecompliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance fromwww.ic.gc.ca.This device has been designed to operate with the antennas listed in Table 7 on page 14, having a maximum gain of -0.5 dBi. Antennasnot included in Table 7 on page 14 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The requiredantenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with anyother antenna or transmitter.ISED NOTICE:The device CYBT-423028-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets therequirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) Thisdevice may not cause harmful interference, and (2) This device must accept any interference received, including interference thatmay cause undesired operation.L'appareil CYBT-423028-02, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond auxexigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditionssuivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, ycompris les interférences pouvant entraîner un fonctionnement indésirable.ISED INTERFERENCE STATEMENT FOR CANADAThis device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s).Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept anyinterference, including interference that may cause undesired operation of the device.Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte delicence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateurde l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonction-nement.ISED RADIATION EXPOSURE STATEMENT FOR CANADAThis equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé. LABELING REQUIREMENTS:The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visiblelabel on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well asthe ISED Notices above. The IC identifier is TBD. In any case, the end product must be labeled in its exterior with "Contains IC: TBD".Le fabricant d'équipement d'origine (OEM) doit s'assurer que les exigences d'étiquetage ISED sont respectées. Cela comprend uneétiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Cypress Semiconductor IC approprié pour ce produitainsi que l'avis ISED ci-dessus. L'identificateur IC est TBD. En tout cas, le produit final doit être étiqueté dans son extérieur avec"Contient IC: TBD".

Document Number: 002-23238 Rev. PRELIMINARY Page 39 of 45PRELIMINARY CYBT-423028-02European Declaration of ConformityHereby, Cypress Semiconductor declares that the Bluetooth module CYBT-423028-02 complies with the essential requirements andother relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive2014, the end-customer equipment should be labeled as follows:All versions of the CYBT-423028-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus,Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta,Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.MIC JapanMore Part Numbers is certified as a module with certification number TBD. End products that integrate More Part Numbers do notneed additional MIC Japan certification for the end product.End product can display the certification label of the embedded module.

Document Number: 002-23238 Rev. PRELIMINARY Page 40 of 45PRELIMINARY CYBT-423028-02PackagingThe CYBT-423028-02 is offered in tape and reel packaging. Figure 20 details the tape dimensions used for the CYBT-423028-02.Figure 20. CYBT-423028-02 Tape Dimensions (TBD)Figure 21 details the orientation of the CYBT-423028-02 in the tape as well as the direction for unreeling.Figure 21. Component Orientation in Tape and Unreeling Direction (TBD)Table 28. Solder Reflow Peak TemperatureModule Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No. of CyclesCYBT-423028-02 28-pad SMT 260 °C 30 seconds 2Table 29. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2Module Part Number Package MSL CYBT-423028-02 28-pad SMT MSL 3

Document Number: 002-23238 Rev. PRELIMINARY Page 41 of 45PRELIMINARY CYBT-423028-02Figure 22 details reel dimensions used for the CYBT-423028-02.Figure 22. Reel DimensionsThe CYBT-423028-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. Thecenter-of-mass for the CYBT-423028-02 is detailed in Figure 23.Figure 23. CYBT-423028-02 Center of Mass (TBD)

Document Number: 002-23238 Rev. PRELIMINARY Page 42 of 45PRELIMINARY CYBT-423028-02Ordering InformationTable 30 lists the CYBT-423028-02 part number and features. Table 30 also lists the target program for the respective module orderingcodes. Table 31 lists the reel shipment quantities for the CYBT-423028-02.The CYBT-423028-02 is offered in tape and reel packaging. The CYBT-423028-02 ships in a reel size of 500 units. For additional information and a complete list of Cypress Semiconductor Bluetooth products, contact your local Cypress salesrepresentative. To locate the nearest Cypress office, visit our website.Table 30. Ordering InformationOrdering Part NumberMax CPU Speed (MHz)Flash Size (KB)RAM Size (KB)UART I2CSPI I2SPCM PWM ADC Inputs GPIOs Package PackagingCYBT-423028-02 96 1024 512 Yes Yes Yes Yes Yes 6 11 17 28-SMT Tape and ReelTable 31. Tape and Reel Package Quantity and Minimum Order AmountDescription Minimum Reel Quantity Maximum Reel Quantity CommentsReel Quantity 500 500 Ships in 500 unit reel quantities. Minimum Order Quantity (MOQ) 500 – –Order Increment (OI) 500 – –U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134U.S. Cypress Headquarter Contact Info (408) 943-2600Cypress website address http://www.cypress.com

Document Number: 002-23238 Rev. PRELIMINARY Page 43 of 45PRELIMINARY CYBT-423028-02Acronyms Document ConventionsUnits of MeasureTable 32. Acronyms Used in this DocumentAcronym DescriptionBLE Bluetooth Low EnergyBluetooth SIG Bluetooth Special Interest GroupCE European ConformityCSA Canadian Standards AssociationEMI electromagnetic interferenceESD electrostatic dischargeFCC Federal Communications CommissionGPIO general-purpose input/outputISED Innovation, Science and Economic Devel-opment (Canada)IDE integrated design environmentKC Korea CertificationMIC Ministry of Internal Affairs and Communications (Japan)PCB printed circuit boardRX receiveQDID qualification design IDSMTsurface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBsTCPWM timer, counter, pulse width modulator (PWM)TUV Germany: Technischer Überwachungs-Verein (Technical Inspection Association)TX transmitTable 33. Units of MeasureSymbol Unit of Measure°C degree CelsiuskV kilovoltmA milliamperesmm millimetersmV millivoltμA microamperesμm micrometersMHz megahertzGHz gigahertzVvolt

Document Number: 002-23238 Rev. PRELIMINARY Page 44 of 45PRELIMINARY CYBT-423028-02Document History Page Document Title: CYBT-423028-02 EZ-BT™ WICED® ModuleDocument Number: 002-23238Revision ECN Orig. of ChangeSubmission Date Description of Change** DSO 03/06/2018 Preliminary datasheet for CYBT-423028-02 module.

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