Cypress Semiconductor 0737 This product is a Bluetooth wireless EZ-BT WICED SIP Module User Manual CYW20737S 0514

Cypress Semiconductor This product is a Bluetooth wireless EZ-BT WICED SIP Module CYW20737S 0514

Contents

User Manual_CYW20737S - 0514

CYW20737SBluetooth Low EnergySystem-in-Package (SiP) ModuleCypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600Document Number: 002-14888 Rev. *C Revised April 21, 2017The CYW20737S is a compact, highly integrated Bluetooth Low Energy (BLE) system-in-package (SiP) module. The CYW20737SSiP includes an embedded BLE antenna, 24 MHz clock, and 512 Kb EEPROM, so only a minimal set of external components isneeded to create a standalone BLE device.The CYW20737S is designed to accelerate time to market. The Bluetooth stack and several application profiles are built into themodule, allowing customers to focus on their core applications. To further reduce application development time, the CYW20737Sincludes integrated software support, with one-click installation of the complete environment and a one-click compile/build/link/loadcycle. All this, coupled with an ultrasmall form factor and support for a wide voltage range, makes the CYW20737S well suited forvirtually any Bluetooth Smart application.Cypress Part Numbering SchemeCypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.Features■ARM Cortex-M3 microcontroller unit (MCU)■Embedded 512 Kb EEPROM■Broadcom Serial Control (BSC), SPI, and UART interfaces■FCC and CE compliant■RoHS compliant, certified lead- and halogen-free■Moisture Sensitivity Level (MSL) 3 compliant■6.5 mm × 6.5 mm × 1.2 mm Land Grid Array (LGA) 48-pin packageApplicationsProfiles supported in ROM:■Battery status■Blood pressure monitor■Find me■Heart rate monitor■Proximity■Thermometer■Weight scale■Time■Blood glucose monitor■Support for RSA security library■Support for LE Audio■Support for pairing using NFC tagsAdditional profiles supported in RAM:■Blood glucose monitor■Temperature alarm■Location■Other custom profilesTable 1. Mapping Table for Part Number between Broadcom and CypressBroadcom Part Number Cypress Part NumberBCM20737S CYW20737S
Document Number: 002-14888 Rev. *C Page 2 of 24CYW20737SFigure 1. CYW20737S BLE SiP Block DiagramIoT ResourcesCypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for yourdesign, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range ofinformation, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and softwareupdates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://community.cypress.com/).VBAT/VDDIOBCM20737SBluetooth Low EnergySystem-on-Chip withARM ® Cortex™ M3-basedMicroprocessor CoreAntennaBandpassFilter UARTSPI/I2CInfraredADCGPIOsPWM32.768 kHzOscillator(optional)24 MHzXTALEEPROM512 Kb I2CBCM20737SCYW20737SCYW20737S
Document Number: 002-14888 Rev. *C Page 3 of 24CYW20737SContents1. Functional Description .................................................41.1 External Reset .......................................................41.2 32.768 kHz Oscillator ............................................ 42. Pin Map and Signal Descriptions ................................53. Electrical Specifications ............................................ 104. RF Specifications ....................................................... 115. ADC Specifications .................................................... 126. Timing and AC Characteristics .................................136.1 SPI Timing ...........................................................136.2 BSC Interface Timing ..........................................146.3 UART Timing ....................................................... 157. PCB Design and Manufacturing Recommendations 167.1 Pad and Solder Mask Opening Dimensions ........ 167.2 PCB Layout Recommendations .......................... 167.3 PCB Stencil ............................................................... 177.4 Solder Reflow ...................................................... 178. Packaging and Storage Information ......................... 189. Mechanical Information ............................................. 2010. Ordering Information ................................................ 22 Document History .......................................................... 23
Document Number: 002-14888 Rev. *C Page 4 of 24CYW20737S1. Functional Description1.1 External ResetExternal reset timing for the CYW20737S is illustrated in Figure 2.Figure 2. External Reset Timing1.2 32.768 kHz OscillatorThe CYW20737S includes a standard Pierce oscillator. The oscillator circuit includes a comparator with hysteresis on the output to create a single-ended digital output. The hysteresis eliminates chatter when the input is near the comparator threshold (~100 mV). The oscillator circuit can is designed for a 32 kHz or 32.768 kHz crystal oscillator, and can also be driven by an external clock input with a similar frequency. Characteristics for a 32 kHz oscillator are defined in Ta b l e 2 .Table 2. 32 kHz Crystal Oscillator CharacteristicsParameter Symbol Conditions Min. Typ. Max. UnitOutput frequency Foscout – – 32.768 – kHzFrequency tolerance Ftol Crystal-dependent – 100 – ppmStart-up time Tstartup – – – 500 µsCrystal drive level Pdrv For crystal selection 0.5 – – µWCrystal series resistance Rseries For crystal selection – – 70 kCrystal shunt capacitance Cshunt For crystal selection – – 1.3 pFRESET_NPulsewidth>20µsCrystalEnableBasebandResetStartreadingEEPROMandfirmwarebootCrystalwarm‐updelay:~5ms
Document Number: 002-14888 Rev. *C Page 5 of 24CYW20737S2. Pin Map and Signal DescriptionsThe CYW20737S pin map is shown in Figure 3.Figure 3. CYW20737S (TOP View)The signal name, type, and description of each pin in the CYW20737S is listed in Table 3 on page 6. The symbols shown under I/O Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any.
Document Number: 002-14888 Rev. *C Page 6 of 24CYW20737STable 3. Pin DescriptionsPin Name I/O Type Description1GPIO: P27PWM1 IDefault direction: Input.After POR state: Input floating.Drain current: 16 mAAlternate function: MOSI (master and slave) for SPI_22 GND GND GND3 VBAT I Battery supply input.4 GND GND GND5 GND GND GND6 GND GND GND7 GND GND GND8 GND GND GND9 GND GND GND10 Reserved – Leave floating11 GND GND GND12 GND GND GND13 GND GND GND14 GND GND GND15 GND GND GND16 GND GND GND17 GND GND GND18 UART_RX I UART_RX. This pin is pulled low through an internal 10 k resistor.19 UART_TX O, PU UART_TX 20 GND GND GND21 SCL I/O, PU SCL I/O, PU clock signal for an external I2C device22 SDA I/O, PU SDA I/O, PU data signal for an external I2C device23 GND GND GND24 GND GND GND25 GPIO: P1 IDefault direction: Input.After POR state: Input floating.This pin is tied to the WP pin of the embedded EEPROM.Requires an external 10K pull-up26 TMC I Test mode control. Pull this pin high to invoke test mode; leave it floating if not used. This pin is connected to GND through an internal 10 k resistor.27 RESET_N I/O PU Active-low system reset with open-drain output
Document Number: 002-14888 Rev. *C Page 7 of 24CYW20737S28 GPIO: P0 IDefault direction: Input.After POR state: Input floating.Alternate functions:■A/D converter input■Peripheral UART TX (PUART_TX)■MOSI (master and slave) for SPI_2■IR_RX■60Hz_main29 GND GND GND30 GPIO: P3 IDefault direction: Input.After POR state: Input floating.Alternate functions:■Peripheral UART CTS (PUART_CTS)■SPI_CLK (master and slave) for SPI_231 GPIO: P2 IDefault direction: Input.After POR state: Input floating.Alternate functions:■Peripheral UART RX (PUART_RX)■SPI_CS (slave only) for SPI_2■SPI_MOSI (master only) for SPI_232 GPIO: P4 IDefault direction: Input.After POR state: Input floating.Alternate functions:■Peripheral UART RX (PUART_RX)■MOSI (master and slave) for SPI_2.■IR_TX33 GPIO: P8 IDefault direction: Input.After POR state: Input floating.Alternate functions: A/D converter input.34 GPIO: P33 IDefault direction: Input.After POR state: Input floating.Alternate functions:■A/D converter input ■MOSI (slave only) for SPI_2■Auxiliary clock output (ACLK1)■Peripheral UART RX (PUART_RX)Table 3. Pin Descriptions (Cont.)Pin Name I/O Type Description
Document Number: 002-14888 Rev. *C Page 8 of 24CYW20737S35 GPIO: P32 IDefault direction: Input.After POR state: Input floating.Alternate functions:■A/D converter input■SPI_CS (slave only) for SPI_2.■Auxiliary clock output (ACLK0)■Peripheral UART TX (PUART_TX)36 GPIO: P25 IDefault direction: Input.After POR state: Input floating.Alternate functions:■MISO (master and slave) for SPI_2■Peripheral UART RX (PUART_RX)37 GPIO: P24 IDefault direction: Input.After POR state: Input floating.Alternate functions:■SPI_CLK (master and slave) for SPI_2■Peripheral UART TX (PUART_TX)38 NC NC No Connection (N/C).39GPIO: P13PWM3 IDefault Direction: InputAfter POR State: Input FloatingDrain current: 16 mAAlternate function: A/D converter inputGPIO: P28PWM2 IDefault direction: Input.After POR state: Input floating.Drain current: 16 mAAlternate functions:■A/D converter input■LED1■IR_TX40GPIO: P14PWM2 IDefault direction: Input.After POR state: Input floating.Alternate function: A/D converter input GPIO: P38 IDefault direction: Input.After POR state: Input floating.Alternate functions:■A/D converter input■MOSI (master and slave) for SPI_2■IR_TX41 GPIO: P15 IDefault direction: Input.After POR state: Input floating.Alternate functions:■A/D converter input■IR_RX■60 Hz_mainTable 3. Pin Descriptions (Cont.)Pin Name I/O Type Description
Document Number: 002-14888 Rev. *C Page 9 of 24CYW20737S42 GPIO: P26PWM0 IDefault direction: Input.After POR state: Input floating.Drain current: 16 mAAlternate function: SPI_CS (slave only) for SPI_243GPIO: P12 IDefault direction: Input.After POR state: Input floating.Alternate functions:■A/D converter input■XTALO32KXTALO32K OLow-power oscillator (LPO) output.Alternate functions:P12P2644GPIO: P11 IDefault direction: Input.After POR state: Input floating.Alternate functions:■A/D converter input■XTALI32KXTALI32K ILow-power oscillator (LPO) input.Alternate functions:■P11■P2745 GND GND GND46 GND GND GND47 GND GND GND48 GND GND GNDTable 3. Pin Descriptions (Cont.)Pin Name I/O Type Description
Document Number: 002-14888 Rev. *C Page 10 of 24CYW20737S3. Electrical SpecificationsAbsolute maximum ratings are defined in Table 4.Power for the CYW20737S module is provided by the host through the power pins.Based on the current measurements in Table 6 on page 10, CYW20737S peak power values are:■RX: 101.6 mW■TX: 101.6 mW■Sleep mode: 217.8 µW■Deep Sleep mode: 9.1 µWTable 4. Absolute Maximum RatingsParameter Min. Max. UnitSupply power NA 3.63 VStorage temperature –40 125 °CVoltage ripple 0 ±2 %Power supply (VBAT absolute maximum rating) 1.62 3.63 V Table 5. VoltageSymbol Parameter Min. Typ. Max. UnitVBAT Battery voltage 1.62 – 3.63 VTable 6. Current ConsumptionOperating Mode Condition Nominal Maximum UnitReceive Receiver and baseband are both operating, 100% 24.0 28.0 mATransmit Transmitter and baseband are both operating, 100% 24.0 28.0 mASleep Wake in < 5 ms 55.0 60.0 µADeep Sleep Wake on interrupt 2.0 2.5 µANote: All measurements taken at 25°C
Document Number: 002-14888 Rev. *C Page 11 of 24CYW20737S4. RF SpecificationsCYW20737S receiver specifications are defined in Ta b le 7.RF transmitter specifications are defined in Table 8.Table 7. Receiver SpecificationsParameter Mode and Conditions Min. Typ. Max. UnitFrequency range – 2402 – 2480 MHzRX sensitivity (standard) Packets: 200Payload: PRBS 9Length: 37 BytesDirty Transmitter: off.PER: 30.8%– –94 – dBmMaximum input – –10 – – dBmNote: All measurements taken at 3.0V (default voltage)Table 8. Transmitter SpecificationsParameter Min. Typ. Max. UnitTransmitterFrequency rangeaa. This parameter is taken from the Bluetooth 4.0 specification.2402 – 2480 MHzOutput power adjustment range –20 – 4 dBmOutput power – 2 – dBmOutput power variation – 2.5 – dBLO PerformanceInitial carrier frequency tolerance – – ±150 kHzFrequency DriftFrequency drift – – ±50 kHzDrift rate – – 20 kHz/50 µsFrequency DeviationAverage deviation in payload(sequence: 00001111)225 – 275 kHzAverage deviation in payload(sequence: 10101010)185 – – kHzChannel spacing – 2 – MHz
Document Number: 002-14888 Rev. *C Page 12 of 24CYW20737S5. ADC SpecificationsCYW20737S ADC specifications are defined in Ta ble 9.Table 9. ADC SpecificationsParameter Symbol Conditions Min. Typ. Max. UnitNumber of input channels – – – 9 – -Channel switching rate fch –––133.33Kch/sInput signal range Vinp –0–3.63VReference settling time – Charging refsel 7.5 – – µsInput resistance Rinp Effective, single-ended – 500 – kInput capacitance Cinp –––5pFConversion rate Fc– 5.859 – 187 kHzConversion time Tc– 5.35 – 170.7 µsResolution R – 16 BitsAbsolute voltage measurement error – Using on–chip ADC firmware driver–±2–%Current I Iavdd1p2 + Iavdd3p3 ––1mAPower P – – 1.5 – mWLeakage Current Ileakage T = 25°C – – 100 nAPower-up time Tpowerup –––200µsIntegral nonlinearity INL In the guaranteed performance range –1 – 1 LSBaa. LSBs are expressed at the 10-bit level.Differential nonlinearity DNL In the guaranteed performance range–1 – 1 LSBa
Document Number: 002-14888 Rev. *C Page 13 of 24CYW20737S6. Timing and AC Characteristics6.1 SPI TimingSPI interface timing is illustrated in Figure 4 and Figure 5 and defined in Table 10 on page 14.Figure 4. SPI Timing—Modes 0 and 2Figure 5. SPI Timing—Modes 1 and 33SPI_CSNSPI_CLK(Mode0)SPI_MOSI ‐FirstBitSPI_MISO NotDriven FirstBitSecondBitSecondBitLastbitLastbit126SPI_CLK(Mode2)NotDriven‐543SPI_CSNSPI_CLK(Mode1)SPI_MOSI ‐InvalidbitSPI_MISO NotDriven InvalidbitFirstbitFirstbitLastbitLastbit126‐NotDrivenSPI_CLK(Mode3)54
Document Number: 002-14888 Rev. *C Page 14 of 24CYW20737S6.2 BSC Interface TimingBSC interface timing is illustrated in Figure 6 and is defined in Tabl e 11 .Figure 6. BSC Interface TimingTable 10. SPI Interface Timing SpecificationsReference Characteristics Min. Typ. Max.1 Time from CSN asserted to first clock edge 1 SCK 100 2 Master setup time – 1/2SCK –3 Master hold time 1/2SCK - –4 Slave setup time – 1/2 SCK –5 Slave hold time 1/2 SCK – –6 Time from last clock edge to CSN deasserted SCK 10 SCK 100Table 11. BSC Interface Timing SpecificationsReference Characteristics Min. Max. Unit1 Clock frequency – 100, 400, 800, 1000 kHz2 START condition setup time 650 – ns3 START condition hold time 280 – ns4 Clock low time 650 – ns5 Clock high time 280 – ns6 Data input hold time 0 – ns7 Data input setup time 100 – ns8 STOP condition setup time 280 – ns9 Output valid from clock – 400 ns10 Bus free time 650 – ns
Document Number: 002-14888 Rev. *C Page 15 of 24CYW20737S6.3 UART TimingUART timing is illustrated in Figure 7 and defined in Table 12.Figure 7. UART TimingTable 12. UART Timing SpecificationsReference Characteristics Min. Max. Unit1 Delay time, UART_CTS_N low to UART_TXD valid – 24 Baudout cycles2 Setup time, UART_CTS_N high before midpoint of stop bit – 10 ns3 Delay time, midpoint of stop bit to UART_RTS_N high – 2 Baudout cycles
Document Number: 002-14888 Rev. *C Page 16 of 24CYW20737S7. PCB Design and Manufacturing Recommendations7.1 Pad and Solder Mask Opening DimensionsCYW20737S pad and solder mask opening dimensions are defined in Table 13.7.2 PCB Layout RecommendationsThe following layout recommendations are referenced to Figure 8 on page 16.■Connect to system ground from side D of the module (pins 13–22).■The L-shaped ground plane is required for the embedded BLE antenna. Keep the GND continuous. Do not cut off the GND shape to accommodate trace routes.■An L-shaped ground plane is required. If the L-shaped GND plane is located on the top layer of the PCB, do not place components on the ground plane. If this cannot be avoided, move the L-shaped ground plane to another layer.■Antenna efficiency of 31–41% can be achieved based on the layout in Figure 8 on page 16 and the dimensions listed below. Following these layout recommendations is expected to yield 50+ meters of usable range; deviating from these recommendations may reduce the range of the antenna.❐D: 4.5 mm (typical)❐G, H, S: 3 mm (typical)❐L: 3 mm (minimum)❐W: 0.4 mm (typical)■Route signal traces out of the module from side C (between pins 27 and 30) or side D (between pins 16 and 19) of the module. Traces can be overlapped to avoid routing through the keep-out area.■Do not route traces from side A or side B.Figure 8. PCB Layout Example Table 13. Pad and Solder Mask DimensionsPad Type Pad Dimensions Solder Mask Opening Dimensions UnitType A 0.6 × 0.25 0.7 × 0.35mmType B 0.55 × 0.3 0.65 × 0.4Type C 0.4 × 0.4 0.5 × 0.5
Document Number: 002-14888 Rev. *C Page 17 of 24CYW20737S7.3 PCB StencilThe recommended PCB stencil is shown in Figure 9 (all measurements in mm). Use an unsolder mask to set the module footprint.Figure 9. CYW20737S Stencil (Bottom View)7.4 Solder ReflowThe recommended solder reflow profile for the CYW20737S is defined in Figure 10.Figure 10. Solder Reflow Profile245°C217°C200°C150°CTiTemperaturePre‐Heating:90~120sec. Soldering:60~90sec.
Document Number: 002-14888 Rev. *C Page 18 of 24CYW20737S8. Packaging and Storage InformationThe CYW20737S is available in a tape and reel package and is shipped in an ESD-protected moisture-resistant (MSL-3) bag as shown in Figure 11. The storage temperature range is –40°C to +125°C.Figure 11. CYW20737S ESD/Moisture PackagingThe moisture sensitivity label on the CYW20737S shipping bag is shown in Figure 12 on page 19.
Document Number: 002-14888 Rev. *C Page 19 of 24CYW20737SFigure 12. CYW20737S Moisture Sensitivity LabelFigure 13 shows the location of pin 1 on the CYW20737S relative to its orientation on the tape packaging.Figure 13. CYW20737S Tape and Reel Pin 1 Location
Document Number: 002-14888 Rev. *C Page 20 of 24CYW20737S9. Mechanical InformationPackage dimensions for the CYW20737S are shown in Figure 14.Figure 14. CYW20737S Package DimensionsAdditional CYW20737S package dimensions are shown in Figure 15 on page 21.
Document Number: 002-14888 Rev. *C Page 21 of 24CYW20737SFigure 15. CYW20737S Pin Dimensions (Bottom View)
Document Number: 002-14888 Rev. *C Page 22 of 24CYW20737S10. Ordering InformationTable 14. Ordering InformationPart Number Package Operating Temperature HumidityCYW20737S 48-pin LGA –40°C to +85°C 95% max., noncondensing
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Document Number: 002-14888 Rev. *C Page 23 of 24CYW20737SDocument HistoryDocument Title: CYW20737S Bluetooth Low Energy System-in-Package (SiP) ModuleDocument Number: 002-14888Revision ECN Orig. of ChangeSubmission Date Description of Change** – – 09/26/2014 20737S-DS100-R: Initial release*A – UTSV 11/06/201520737S-DS101-R:Updated•Table 5 on page 14*B 5444054 UTSV 09/23/2016 Updated to Cypress Template*C 5688156 AESATMP7 04/21/2017 Updated Cypress Logo and Copyright.
Document Number: 002-14888 Rev. *C Revised April 21, 2017 Page 24 of 24CYW20737S© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countriesworldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or otherintellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypresshereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, tomodify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (asprovided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilationof the Software is prohibited.TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWAREOR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extentpermitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of anyproduct or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It isthe responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress productsare not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices orsystems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of thedevice or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonablyexpected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and otherliabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress inthe United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.Sales, Solutions, and Legal Information Worldwide Sales and Design SupportCypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.ProductsARM® Cortex® Microcontrollers cypress.com/armAutomotive cypress.com/automotiveClocks & Buffers cypress.com/clocksInterface cypress.com/interfaceInternet of Things cypress.com/iotMemory cypress.com/memoryMicrocontrollers cypress.com/mcuPSoC cypress.com/psocPower Management ICs cypress.com/pmicTouch Sensing cypress.com/touchUSB Controllers cypress.com/usbWireless Connectivity cypress.com/wirelessPSoC®SolutionsPSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6Cypress Developer CommunityForums | WICED IoT Forums | Projects | Video | Blogs |Training | ComponentsTechnical Supportcypress.com/support24

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